View PIC16C641-04ITQ_244878.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PIC16C64X & PIC16C66X
8-Bit EPROM Microcontrollers with Analog Comparators
Devices included in this data sheet:
* * * * PIC16C641 PIC16C642 PIC16C661 PIC16C662
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3 RA4/T0CKI RA5 VSS OSC1/CLKIN OSC2/CLKOUT RC0 RC1 RC2 RC3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
High Performance RISC CPU:
* Only 35 instructions to learn * All single-cycle instructions (200 ns), except for program branches which are two-cycle * Operating speed: - DC - 20 MHz clock input - DC - 200 ns instruction cycle Device PIC16C641 PIC16C642 PIC16C661 PIC16C662 Program Memory x14 2K 4K 2K 4K Data Memory x8 128 176 128 176
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5 RC4
PDIP, Windowed CERDIP
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3 RA4/T0CKI RA5 RE0/RD RE1/WR RE2/CS VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0 RC1 RC2 RC3 RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7 RC6 RC5 RC4 RD3/PSP3 RD2/PSP2
PIC16C64X PIC16C66X
* Interrupt capability * 8-level deep hardware stack * Direct, Indirect and Relative addressing modes
Peripheral Features:
* Up to 33 I/O pins with individual direction control * High current sink/source for direct LED drive * Analog comparator module with: - Two analog comparators - Programmable on-chip voltage reference (VREF) module - Programmable input multiplexing from device inputs and internal voltage reference - Comparator outputs can be output signals * Timer0: 8-bit timer/counter with 8-bit programmable prescaler
Special Microcontroller Features:
* Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Brown-out Reset * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code protection * Power saving SLEEP mode * Selectable oscillator options * Serial in-circuit programming (via two pins)
* Four user programmable ID locations * Program Memory Parity Error checking circuitry with Parity Error Reset (PER) * CMOS Technology: * Low-power, high-speed CMOS EPROM technology * Fully static design * Wide operating voltage range: 3.0V to 6.0V * Commercial, Industrial and Automotive temperature ranges * Low power consumption - < 2.0 mA @ 5.0V, 4.0 MHz - 15 A typical @ 3.0V, 32 kHz - < 1.0 A typical standby current @ 3.0V
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 1
PIC16C64X & PIC16C66X
Pin Diagrams (Cont.'d) TQFP
RC6 RC5 RC4 RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3 RC2 RC1 NC
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
RC7 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3
1 2 3 4 5 6 7 8 9 10 11
PIC16C66X
NC RC0 OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS RE1/WR RE0/RD RA5 RA4/T0CKI
12 1314 15 16 17 1819 20 21 22
RA4/T0CKI RA5 RE0/RD RE1/WR RE2/CS VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0 NC
6 5 4 3 2 1 44 43 42 4140 39 38 37 36 35 34 33 32 31 30 16 29 17 18 19 20 21 2223 24 2526 27 28 7 8 9 10 11 12 13 14 15
RA3/AN3 RA2/AN2/VREF RA1/AN1 RA0/AN0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC
RA3/AN3 RA2/AN2/VREF RA1/AN1 RA0/AN0 MCLR/VPP RB7 RB6 RB5 RB4 NC NC
PLCC
PIC16C66X
RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7
NC RC6 RC5 RC4 RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3 RC2 RC1
DS30559A-page 2
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Table of Contents 1.0 General Description .......................................................................................................................................... 5 2.0 PIC16C64X & PIC16C66X Device Varieties .................................................................................................... 7 3.0 Architectural Overview...................................................................................................................................... 9 4.0 Memory Organization ..................................................................................................................................... 17 5.0 I/O Ports.......................................................................................................................................................... 29 6.0 Timer0 Module................................................................................................................................................ 41 7.0 Comparator Module ........................................................................................................................................ 47 8.0 Voltage Reference Module ............................................................................................................................. 53 9.0 Special Features of the CPU .......................................................................................................................... 55 10.0 Instruction Set Summary ................................................................................................................................ 73 11.0 Development Support ..................................................................................................................................... 87 12.0 Electrical Specifications .................................................................................................................................. 91 13.0 Device Characterization Information............................................................................................................. 103 14.0 Packaging Information .................................................................................................................................. 105 Appendix A: Enhancements...................................................................................................................................... 115 Appendix B: Compatibility ......................................................................................................................................... 115 Appendix C: What's New .......................................................................................................................................... 116 Appendix D: What's Changed ................................................................................................................................... 116 Appendix E: PIC16/17 Microcontrollers ..................................................................................................................... 117 Pin Compatibility ......................................................................................................................................................... 125 Index ........................................................................................................................................................................... 127 List of Examples.......................................................................................................................................................... 129 List of Figures.............................................................................................................................................................. 129 List of Tables............................................................................................................................................................... 130 On-Line Support.......................................................................................................................................................... 131 Reader Response ....................................................................................................................................................... 132 PIC16C64X & PIC16C66X Product Identification System .......................................................................................... 135
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 3
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 4
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
1.0 GENERAL DESCRIPTION
PIC16C64X & PIC16C66X devices are 28-pin and 40-pin EPROM-based members of the versatile PIC16CXXX family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers. All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXXX family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16CXXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in its class. The PIC16C641 has 128 bytes of RAM and the PIC16C642 has 176 bytes of RAM. Both devices have 22 I/O pins, and an 8-bit timer/counter with an 8-bit programmable prescaler. In addition, they have two analog comparators with a programmable on-chip voltage reference module. Program Memory has internal parity error detection circuitry with a Parity Error Reset. The comparator module is ideally suited for applications requiring a low-cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc.). The PIC16C661 has 128 bytes of RAM and the PIC16C662 has 176 bytes of RAM. Both devices have 33 I/O pins, and an 8-bit timer/counter with an 8-bit programmable prescaler. They also have an 8-bit Parallel Slave Port. In addition, the devices have two analog comparators with a programmable on-chip voltage reference module. Program Memory has internal parity error detection circuitry with a Parity Error Reset. The comparator module is ideally suited for applications requiring a low-cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc.). PIC16CXXX devices have special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power saving. The user can wake-up the chip from SLEEP through several external and internal interrupts and resets. A highly reliable Watchdog Timer (WDT) with its own on-chip RC oscillator provides protection against software lock-up. A UV-erasable CERDIP-packaged version is ideal for code development while the cost-effective One-Time Programmable (OTP) version is suitable for production in any volume. The PIC16CXXX series fit perfectly in applications ranging from battery chargers to low-power remote sensors. The EPROM technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high-performance, ease of use, and I/O flexibility make the PIC16C64X & PIC16C66X very versatile.
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for PIC16C5X can be easily ported to the PIC16C64X & PIC16C66X (Appendix B).
1.2
Development Support
PIC16C64X & PIC16C66X devices are supported by the complete line of Microchip Development tools, including: * MPLAB Integrated Development Environment including MPLAB-Simulator. * MPASM Universal Assembler and MPLAB-C Universal C compiler. * PRO MATE II and PICSTART Plus device programmers. * PICMASTER In-circuit Emulator System * fuzzyTECH-MP Fuzzy Logic Development Tools * DriveWay Visual Programming Tool Please refer to Section 11.0 for more details about these and other Microchip development tools.
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 5
TABLE 1-1:
DS30559A-page 6 Clock
n (M ) Hz
Memory
ry
Peripherals
Features
M
a
xim
um
e Fr
qu
en
cy
o
fO
p
at er
io
Pr
M em or y (b e yt
r og
s)
am
M
em
o
l Vo ve
ru er pt u So
ta P
rc
ge t or
es
lts
)
M
Da ta
E
128 176 128 176 TMR0 2 Yes Yes 5 33 3.0-6.0 Yes TMR0 2 Yes Yes 5 33 3.0-6.0 Yes TMR0 2 Yes 4 22 3.0-6.0 TMR0 2 Yes 4 22 3.0-6.0
O PR
Ti
Co
m
er
m
M
pa
o
ra
l du
t
e(
(s or )
s)
In
In
t Pa
t
n er
al l ra le l
f Re a Sl
er
e
e nc
I/O
Pi
Vo g lta
ns
e
R
an
ge
o (V
se
a ck ge s
t
Br
o
wn
Pa
ou
e tR
PIC16C641 20 20 20 4K 2K 4K
20
2K
Yes 28-pin PDIP, SOIC, Windowed CDIP Yes 28-pin PDIP, SOIC, Windowed CDIP 40-pin PDIP, Windowed CDIP; 44-pin PLCC, TQFP 40-pin PDIP, Windowed CDIP; 44-pin PLCC, TQFP
PIC16C64X & PIC16C66X
PIC16C642
PIC16C64X & PIC16C66X DEVICE FEATURES
Preliminary
PIC16C661
PIC16C662
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability. All PIC16CXXX Family devices use serial programming with clock pin RB6 and data pin RB7.
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
2.0 PIC16C64X & PIC16C66X DEVICE VARIETIES
2.3 Quick-Turnaround-Production (QTP) Devices
A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in the Product Identification System page at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes. Microchip's PICSTART(R) Plus and PRO MATE(R) II programmers both support programming of the PIC16C64X & PIC16C66X.
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details.
2.4
Serialized Quick-TurnaroundProduction (SQTPSM) Devices
2.2
One-Time-Programmable (OTP) Devices
Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.
The availability of OTP devices is especially useful for customers who need flexibility for frequent code updates and small volume applications. In addition to the program memory, the configuration bits must also be programmed.
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 7
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 8
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16C64X & PIC16C66X devices can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C64X & PIC16C66X use a Harvard architecture in which program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than an 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35) execute in a single cycle (200 ns @ 20 MHz) except for program branches, which require two cycles. The PIC16C641 and PIC16C661 both address 2K x 14 on-chip program memory while the PIC16C642 and PIC16C662 address 4K x 14. All program memory is internal. PIC16C64X & PIC16C66X devices can directly or indirectly address their register files or data memory. All special function registers including the program counter are mapped in the data memory. These devices have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16C64X & PIC16C66X simple yet efficient. In addition, the learning curve is reduced significantly. PIC16C64X & PIC16C66X devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift, and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, bit in subtraction. See the SUBLW and SUBWF instructions for examples.
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 9
PIC16C64X & PIC16C66X
FIGURE 3-1: PIC16C641/642 BLOCK DIAGRAM
PIC16C641 has 2K x 14 Program Memory and 128 x 8 RAM PIC16C642 has 4K x 14 Program Memory and 176 x 8 RAM
13 Program Counter EPROM Program Memory 8 Level Stack (13-bit) RAM File Registers 9 Addr MUX 8 Direct Addr 7 Indirect Addr Timer0
+
Data Bus
8
Voltage Reference
Comparator RA0/AN0
+
RA1/AN1 RA2/AN2/VREF RA3/AN3
Program Bus
14 Instruction reg RAM Bank Select
FSR reg STATUS reg
RA4/T0CKI 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Parity Error Reset PORTB RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 PORTC RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RA5 ALU MUX
PORTA
W reg
MCLR
VDD, VSS
DS30559A-page 10
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 3-2: PIC16C661/662 BLOCK DIAGRAM
PIC16C661 has 2K x 14 Program Memory and 128 x 8 RAM PIC16C662 has 4K x 14 Program Memory and 176 x 8 RAM
13 Program Counter EPROM Program Memory 8 Level Stack (13-bit)
Data Bus
8
Voltage Reference
RAM File Registers 9 Addr MUX 8 Indirect Addr
Comparator RA0/AN0
+
RA1/AN1 RA2/AN2/VREF RA3/AN3
Program Bus
14 Instruction reg RAM Bank Select Direct Addr 7
+
FSR reg STATUS reg
Timer0
RA4/T0CKI 3 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Parity Error Reset PORTB RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 PORTC RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 ALU PORTA MUX
Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT
W reg RA5
MCLR
VDD, VSS
Parallel Slave Port
PORTE RE0/RD RE1/WR PORTD RE2/CS
RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 11
PIC16C64X & PIC16C66X
TABLE 3-1:
Name OSC1/CLKIN OSC2/CLKOUT
PIC16C641/642 PINOUT DESCRIPTION
Pin # 9 10 I/O/P Type I O Buffer Type Description
MCLR/VPP
1
I/P
RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3 RA4/T0CKI RA5
2 3 4 5 6 7
I/O I/O I/O I/O I/O I/O
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 VSS VDD Legend:
21 22 23 24 25 26 27 28
I/O I/O I/O I/O I/O I/O I/O I/O
ST/CMOS Oscillator crystal input or external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. ST Analog comparator input. ST Analog comparator input. ST Analog comparator input or VREF output. ST Analog comparator input or comparator output. ST Can be selected to be the clock input to the Timer0 timer/counter or a comparator output. Output is open drain type. ST PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. (1) RB0 can also be selected as an external interrupt pin. TTL/ST TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2)
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port.
11 I/O ST 12 I/O ST 13 I/O ST 14 I/O ST 15 I/O ST 16 I/O ST 17 I/O ST 18 I/O ST 8,19 P -- Ground reference for logic and I/O pins. 20 P -- Positive supply for logic and I/O pins. O = output I/O = input/output P = power I = input -- = not used ST = Schmitt Trigger input TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
DS30559A-page 12
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
TABLE 3-2:
Name OSC1/CLKIN OSC2/CLKOUT
PIC16C661/662 PINOUT DESCRIPTION
DIP Pin # 13 14 QFP Pin # 30 31 PLCC Pin # 14 15 I/O/P Type I Buffer Type Description
MCLR/VPP
1
18
2
RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3 RA4/T0CKI
2 3 4 5 6
19 20 21 22 23
3 4 5 6 7
RA5
7
24
8
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7
33 34 35 36 37 38 39 40
8 9 10 11 14 15 16 17
36 37 38 39 41 42 43 44
RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 Legend:
15 32 16 16 35 18 17 36 19 18 37 20 23 42 25 24 43 26 25 44 27 26 1 29 O = output I = input TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used in the Parallel Slave Port Mode (for interfacing to a microprocessor port).
ST/CMOS Oscillator crystal input or external clock source input. O -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. I/O ST Analog comparator input. I/O ST Analog comparator input. I/O ST Analog comparator input or VREF output. I/O ST Analog comparator input or comparator output. I/O ST Can be selected to be the clock input to the Timer0 timer/counter or a comparator output. Output is open drain type. I/O ST PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. (1) I/O RB0 can also be selected as an external TTL/ST interrupt pin. I/O TTL I/O TTL I/O TTL I/O TTL Interrupt on change pin. I/O TTL Interrupt on change pin. (2) I/O Interrupt on change pin. Serial programming TTL/ST clock. (2) I/O Interrupt on change pin. Serial programming TTL/ST data. PORTC is a bi-directional I/O port. I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O ST I/O = input/output P = power -- = not used ST = Schmitt Trigger input
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 13
PIC16C64X & PIC16C66X
Name DIP Pin # QFP Pin # PLCC Pin # I/O/P Type Buffer Type Description PORTD can be a bi-directional I/O port or parallel slave port for interfacing to a microprocessor bus. RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RE0/RD RE1/WR RE2/CS VSS VDD NC Legend: 19 20 21 22 27 28 29 30 38 39 40 41 2 3 4 5 21 22 23 24 30 31 32 33 I/O I/O I/O I/O I/O I/O I/O I/O ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) PORTE is a bi-directional I/O port. RE0/RD read control for parallel slave port. ST/TTL(3) RE1/WR write control for parallel slave port. RE2/CS select control for parallel slave port. ST/TTL(3) -- Ground reference for logic and I/O pins. -- Positive supply for logic and I/O pins. -- Not Connected. ST/TTL(3)
Note 1: 2: 3:
8 25 9 I/O 9 26 10 I/O 10 27 11 I/O 12,31 6,29 13,34 P 11,32 7,28 12,35 P -- 12,13, 1,17 -- 33,34 28,40 O = output I/O = input/output P = power I = input -- = not used ST = Schmitt Trigger input TTL = TTL input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used in the Parallel Slave Port Mode (for interfacing to a microprocessor port).
DS30559A-page 14
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-3. An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3, and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register (IR)" in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-3:
CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC
PC PC+1 PC+2 Internal phase clock
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC2/CLKOUT (RC mode)
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
Tcy0 Tcy1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 Tcy2 Tcy3 Tcy4 Tcy5
1. MOVLW 55h 2. MOVWF PORTB 3. CALL SUB_1 4. BSF
Fetch 1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 15
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 16
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.0
4.1
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 4-2:
PIC16C642/662 PROGRAM MEMORY MAP AND STACK
The PIC16C64X & PIC16C66X have a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16C641 and PIC16C661 only the first 2K x 14 (0000h - 07FFh) is physically implemented. For the PIC16C642 and PIC16C662 only the first 4K x 14 (0000h - 0FFh) is physically implemented. Accessing a location above the 2K or 4K boundary will cause a wrap-around. The reset vector is at 0000h and the interrupt vector is at 0004h (Figure 41 and Figure 4-2). See Section 4.4 for Program Memory paging.
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2
Stack Level 8 Reset Vector
FIGURE 4-1:
PIC16C641/661 PROGRAM MEMORY MAP AND STACK
PC<12:0> 13 User Memory Space
0000h
CALL, RETURN RETFIE, RETLW
Interrupt Vector On-chip Program Memory Page0
Stack Level 1 Stack Level 2
0004h 0005h
Stack Level 8 Reset Vector User Memory Space
On-chip Program Memory 0000h Page1
07FFh 0800h
0FFFh 1000h
Interrupt Vector
0004h 0005h
1FFFh TEST Configuration Word 2000h 2007h 3FFFh
On-chip Program Memory 07FFh 0800h
TEST
1FFFh TEST Configuration Word TEST 2000h 2007h 3FFFh
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 17
PIC16C64X & PIC16C66X
4.2 Data Memory Organization FIGURE 4-3:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(2) PORTE(2) PCLATH INTCON PIR1 INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD(2) TRISE(2) PCLATH INTCON PIE1 PCON The data memory (Figure 4-4) is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected when bit RP0 (STATUS<5>) is cleared. Bank 1 is selected when the RP0 bit is set. The Special Function Registers are located in the first 32 locations of each Bank. Register locations A0h-EFh (Bank 1) are general purpose registers implemented as static RAM. Some special function registers are mapped in Bank 1. 4.2.1 GENERAL PURPOSE REGISTER FILE
PIC16C641/661 DATA MEMORY MAP
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
The register file is organized as 176 x 8 for the PIC16C642/662, and 128 x8 for the PIC16C641/661. Each is accessed either directly, or indirectly through the File Select Register FSR (Section 4.5).
CMCON General Purpose Register
VRCON General Purpose Register
BFh C0h EFh F0h FFh
Mapped in Page 0 7Fh Bank 0 Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register. 2: Not implemented on the PIC16C641.
DS30559A-page 18
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 4-4:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(2) PORTE(2) PCLATH INTCON PIR1 INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD(2) TRISE(2) PCLATH INTCON PIE1 PCON
PIC16C642/662 DATA MEMORY MAP
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register EFh Mapped in Bank 0 F0h FFh Bank 0 Bank 1
4.2.2
SPECIAL FUNCTION REGISTERS
The special function registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device (Table 4-1). These registers are static RAM. The special function registers can be classified into two sets (core and peripheral). The special function registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
CMCON
VRCON
General Purpose Register
7Fh
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: Not implemented on the PIC16C642.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 19
PIC16C64X & PIC16C66X
TABLE 4-1:
Address Name
SPECIAL FUNCTION REGISTERS
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR, PER Value on all other resets(1)
Bank 0 00h 01h 02h 03h 04h 05h 06h 06h 06h 06h 0Ah 0Bh 0Ch 1Fh Bank 1 80h 81h 82h 83h 84h 85h 86h 86h 86h 86h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh-9Eh 9Fh Note INDF OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD(3) TRISE(3) PCLATH INTCON PIE1 Unimplemented PCON Unimplemented VRCON VREN VROE VRR -- VR3 VR2 VR1 VR0 MPEEN -- -- -- -- PER POR BOR Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx RBPU IRP(2) -- INTEDG RP1(2) -- T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C 1111 1111 1111 1111 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --11 1111 --11 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 PSPMODE INTE -- -- RBIE -- TRISE2 T0IF -- TRISE1 INTF -- TRISE0 RBIF -- 0000 -111 0000 -111 ---0 0000 ---0 0000 0000 000x 0000 000x 00-- ---- 00-- ----- -- -- -- u--- -qqq u--- -uuu 000- 0000 000- 0000 Write buffer for upper 5 bits of program counter Program Counter's (PC) Least Significant Byte Indirect data memory address pointer PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register IBF -- GIE PSPIE(4) OBF -- PEIE CMIE IBOV -- T0IE -- INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(3) PORTE(3) PCLATH INTCON PIR1 CMCON Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP(2) -- RP1(2) -- RP0 TO PD Z DC C Indirect data memory address pointer PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read -- -- GIE PSPIF(4) C2OUT -- -- PEIE CMIF C1OUT -- -- T0IE -- -- -- INTE -- -- -- RBIE -- CIS RE2 T0IF -- CM2 RE1 INTF -- CM1 RE0 RBIF -- CM0 Write buffer for upper 5 bits of program counter xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --xx 0000 --xu 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu ---- -xxx ---- -uuu ---0 0000 ---0 0000 0000 000x 0000 000u 00-- ---- 00-- ----- -- 00-- 0000 00-- 0000
0Dh-1Eh Unimplemented
Legend: - = unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented 1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: The IRP and RP1 bits are reserved, always maintain these bits clear. 3: The PORTD, PORTE, TRISD, and TRISE registers are not implemented on the PIC16C641/642. 4: Bits PSPIE and PSPIF are reserved on the PIC16C641/642, always maintain these bits clear.
DS30559A-page 20
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 4-5, contains the arithmetic status of the ALU, the RESET status, and the bank select bits for data memory. The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000uu1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF, and MOVWF instructions are used to alter the STATUS register because these instructions do not affect any status bit. For other instructions, not affecting any status bits, see the "Instruction Set Summary." Note 1: The IRP and RP1 bits (STATUS<7:6>) are reserved on the PIC16C64X & PIC16C66X and should be maintained clear. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. Note 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
FIGURE 4-5:
R/W-0 IRP bit7
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
R/W-0 RP1
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) Bit IRP is reserved on the PIC16C64X & PIC16C66X, always maintain this bit clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. Bit RP1 is reserved on the PIC16C64X & PIC16C66X, always maintain this bit clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 21
PIC16C64X & PIC16C66X
4.2.2.2 OPTION REGISTER Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT. The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 4-6:
R/W-1 RBPU bit7
OPTION REGISTER (ADDRESS 81h)
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
R/W-1 INTEDG
R= Readable bit W= Writable bit U= Unimplemented bit, read as `0' - n= Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
DS30559A-page 22
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The INTCON register is a readable and writable register which contains the various enable and flag bits for all non-peripheral interrupt sources.
FIGURE 4-7:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0
R/W-0 PEIE
R= Readable bit W= Writable bit U= Unimplemented bit, read as `0' - n= Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (See Section 5.2 to clear interrupt) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 23
PIC16C64X & PIC16C66X
4.2.2.4 PIE1 REGISTER This register contains the individual enable bits for the comparator and Parallel Slave Port interrupts.
FIGURE 4-8:
R/W-0 PSPIE(1) bit7
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 CMIE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit0
R= Readable bit W= Writable bit U= Unimplemented bit, read as `0' - n= Value at POR reset
bit 7:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt
bit 6:
bit 5-0: Unimplemented: Read as '0' Note 1: Bit PSPIE is reserved on the PIC16C641/642, always maintain this bit clear.
DS30559A-page 24
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the comparator and Parallel Slave Port interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
FIGURE 4-9:
R/W-0 PSPIF(1) bit7
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 CMIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit0
R= Readable bit W= Writable bit U= Unimplemented bit, read as `0' - n= Value at POR reset
bit 7:
PSPIF(1): Parallel Slave Port Interrupt Flag bit 1 = A read or write operation has taken place (must be cleared in software) 0 = No read or write operation has taken place CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed
bit 6:
bit 5-0: Unimplemented: Read as '0' Note 1: Bit PSPIF is reserved on the PIC16C641/642, always maintain this bit clear.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 25
PIC16C64X & PIC16C66X
4.2.2.6 PCON REGISTER Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is cleared, indicating a brown-out has occurred. The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming the BODEN bit in the Configuration word). The PCON register contains flag bits to differentiate between a Power-on Reset (POR), an external MCLR reset, WDT reset, Brown-out Reset (BOR), and Parity Error Reset (PER). The PCON register also contains a status bit, MPEEN, which reflects the value of the MPEEN bit in Configuration Word. See Table 9-4 for status of these bits on various resets.
FIGURE 4-10: PCON REGISTER (ADDRESS 8Eh)
R-U MPEEN bit7 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 PER R/W-0 POR R/W-u BOR bit0
R= Readable bit W= Writable bit U= Unimplemented bit, read as `0' - n= Value at POR reset
bit 7:
MPEEN: Memory Parity Error Circuitry Status bit Reflects the value of Configuration Word bit, MPEEN PER: Memory Parity Error Reset Status bit 1 = No error occurred 0 = Program memory fetch parity error occurred (must be set in software after a Parity Error Reset occurs) POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
bit 6-3: Unimplemented: Read as '0' bit 2:
bit 1:
bit 0:
DS30559A-page 26
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.3 PCL and PCLATH
4.3.2 STACK The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is readable and writable. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-11 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). PIC16C64X & PIC16C66X devices have an 8 level deep x 13-bit wide hardware stack (Figure 4-2). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. Note 2: There are no instructions mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.
FIGURE 4-11: LOADING OF PC IN DIFFERENT SITUATIONS
PCH 12 PC 5 PCLATH<4:0> 8 8 7 PCL 0 Instruction with PCL as Destination ALU result
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
4.4
Program Memory Paging
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556).
PIC16C642 and PIC16C662 devices have 4K of program memory, but the CALL and GOTO instructions only have an 11-bit address range. This 11-bit address range allows a branch within a 2K program memory page size. To allow CALL and GOTO instructions to address the entire 4K program memory address range, there must be another bit to specify the program memory page. This paging bit comes from the PCLATH<3> bit (Figure 4-11). When doing a CALL or GOTO instruction, the user must ensure that this page select bit (PCLATH<3>) is programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<3> bit is not required for the return instructions (which POPs the address from the stack). Note: The PIC16C64X & PIC16C66X ignore the PCLATH<4> bit, which is used for program memory pages 2 and 3 (1000h - 1FFFh). The use of PCLATH<4> as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 27
PIC16C64X & PIC16C66X
4.5 Indirect Addressing, INDF, and FSR Registers
A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 4-1.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the file select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a nooperation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-12. However, bit IRP is not used in the PIC16C64X & PIC16C66X.
EXAMPLE 4-1:
movlw movwf clrf incf btfss goto
INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no goto next ;yes continue
NEXT
CONTINUE:
FIGURE 4-12: DIRECT/INDIRECT ADDRESSING
Direct Addressing
(1)RP1
Indirect Addressing
0 IRP(1) 7 FSR register 0
RP0
6
from opcode
bank select
location select 00 00h 01 10 11
bank select 00h
location select
not used Data Memory
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 4-3 and Figure 4-4. Note 1: Bits RP1 and IRP are reserved, always maintain these bits clear.
DS30559A-page 28
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
5.0 I/O PORTS
FIGURE 5-1:
Data bus WR Port
The PIC16C641 and PIC16C642 have three ports, PORTA, PORTB, and PORTC. PIC16C661 and PIC16C662 devices have five ports, PORTA through PORTE. Some pins for these I/O ports are multiplexed with alternate functions for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
BLOCK DIAGRAM OF RA1:RA0 PINS
Q VDD
D CK D
Q Q
P
Data Latch I/O Pin
5.1
PORTA and TRISA Registers
PORTA is a 6-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Pin RA4 is multiplexed with the T0CKI clock input. All other RA port pins have Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as input or output. Setting a bit in the TRISA register puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin. Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. The PORTA pins are multiplexed with comparator and voltage reference functions. The operation of these pins are selected by control bits in the CMCON (comparator control register) register and the VRCON (voltage reference control) register. When selected as comparator inputs, these pins will read as '0's.
WR TRIS
N CK Q VSS Analog Input Mode Schmitt Trigger Input Buffer Q EN D TRIS Latch
RD TRIS
RD PORT
To Comparator Note: I/O pins have protection diodes to VDD and VSS.
Note:
On reset, the TRISA register is set to all inputs. The digital inputs are disabled and the comparator inputs are forced to ground to reduce excess current consumption.
TRISA controls the direction of the RA pins, even when they are being used as comparator inputs. The user must make sure to keep the pins configured as inputs when using them as comparator inputs. The RA2 pin will also function as the output for the voltage reference. When in this mode, the VREF pin is a very hi-impedance output. The user must set the TRISA<2> bit and use hi-impedance loads. In one of the comparator modes defined by the CMCON register, pins RA3 and RA4 become outputs of the comparators. The TRISA<4:3> bits must be cleared to enable outputs to use this function.
EXAMPLE 5-1:
CLRF MOVLW MOVWF BSF MOVLW MOVWF PORTA
INITIALIZING PORTA
;Initialize PORTA by ;clearing output latches ;Turn comparators off, ;enable pins for I/O ;Select bank1 ;Value to initialize ;data direction ;Set RA<4:0> as inputs ;TRISA<7:5> are clear
0x07 CMCON STATUS, RP0 0x1F TRISA
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 29
PIC16C64X & PIC16C66X
FIGURE 5-2:
Data bus WR Port D CK D WR TRIS CK
BLOCK DIAGRAM OF RA2 PIN
Q VDD Q Q N Q VSS Analog Input Mode Schmitt Trigger Input Buffer Q EN D RA2 Pin P
Data Latch
TRIS Latch
RD TRIS
RD PORT
To Comparator VROE VREF Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 5-3:
Data bus WR Port D CK D WR TRIS CK
BLOCK DIAGRAM OF RA3 PIN
Comparator Mode = 110 Q Comparator Output Q Q N Q VSS Analog Input Mode Schmitt Trigger Input Buffer Q EN D RA3 Pin VDD P
Data Latch
TRIS Latch
RD TRIS
RD PORT
To Comparator
DS30559A-page 30
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 5-4:
Data bus WR Port D CK D WR TRIS CK
BLOCK DIAGRAM OF RA4 PIN
Comparator Mode = 110 Q Comparator Output Q Q N Q VSS RA4 Pin
Data Latch
TRIS Latch
RD TRIS Q EN RD PORT
Schmitt Trigger Input Buffer D
TMR0 Clock Input
TABLE 5-1:
Name RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3 RA4/T0CKI
PORTA FUNCTIONS
Bit # bit0 bit1 bit2 bit3 bit4 Buffer Type ST ST ST ST ST Function Input/output or comparator input. Input/output or comparator input. Input/output or comparator input or VREF output. Input/output or comparator input/output. Input/output or external clock input for TMR0 or comparator output. Output is open drain type. Input/output.
RA5 bit5 ST Legend: ST = Schmitt Trigger input
TABLE 5-2:
Address Name 05h 85h 1Fh 9Fh Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 0000 1111 0000 0000
-- -- RA5 RA4 RA3 RA2 RA1 RA0 --xx 0000 --uu PORTA TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 CMCON C2OUT C1OUT -- -- CIS CM2 CM1 CM0 00-- 0000 00-VRCON VREN VROE VRR -- VR3 VR2 VR1 VR0 000- 0000 000x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 31
PIC16C64X & PIC16C66X
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s). Reading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RBIF interrupt (flag latched in (INTCON<0>)). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. (See AN552 in the Microchip Embedded Control Handbook.) The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
FIGURE 5-6:
BLOCK DIAGRAM OF RB3:RB0 PINS
VDD weak P pull-up Data Latch D Q CK I/O pin(1) Q
RBPU(2)
Data bus WR Port
FIGURE 5-5:
BLOCK DIAGRAM OF RB7:RB4 PINS
VDD WR TRIS weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
D CK
RBPU(2)
TTL Input Buffer
Data bus WR Port
RD TRIS Q RD Port TTL Input Buffer D EN
WR TRIS
CK
RB0/INT ST Buffer ST Buffer RD Port
RD TRIS Q RD Port Set RBIF From other RB7:RB4 pins
Latch D EN Note 1: I/O pins have diode protection to VDD and VSS. 2: TRISB = '1' enables weak pull-up if RBPU = '0' (OPTION<7>).
Q
D EN
RB7:RB6 in serial programming mode
RD Port
Note 1: I/O pins have diode protection to VDD and VSS. 2: TRISB = '1' enables weak pull-up if RBPU = '0' (OPTION<7>).
DS30559A-page 32
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
EXAMPLE 5-2:
CLRF PORTB
INITIALIZING PORTB
; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
BSF MOVLW
STATUS, RP0 0xCF
MOVWF
TRISB
TABLE 5-3:
Name RB0/INT
PORTB FUNCTIONS
Bit # bit0 Buffer Type TTL/ST
(1)
Function
Input/output or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 Input/output pin (with interrupt on change). Internal software programmable TTL/ST(2) weak pull-up. Serial programming clock pin. (2) RB7 bit7 Input/output pin (with interrupt on change). Internal software programmable TTL/ST weak pull-up. Serial programming data pin. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4:
Address Name 06h 86h 81h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets uuuu uuuu 1111 1111 1111 1111
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 Legend: x = unknown, u = unchanged, shaded cells are not used by PORTB.
PORTB TRISB OPTION
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 33
PIC16C64X & PIC16C66X
5.3 PORTC and TRISC Registers FIGURE 5-7:
Data bus WR PORT
PORTC is an 8-bit bi-directional port. Each pin is individually configurable as an input or output through the TRISC register. PORTC pins have Schmitt Trigger input buffers.
PORTC BLOCK DIAGRAM (IN I/O PORT MODE)
D Q
I/O pin(1)
CK
EXAMPLE 5-3:
CLRF PORTC
INITIALIZING PORTC
; ; ; ; ; ; ; ; ; ; Initialize PORTC by clearing output data latches Select Bank 1 Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs
Data Latch
D Q
BSF MOVLW
STATUS, RP0 0xCF
WR TRIS
CK
TRIS Latch
Schmitt Trigger input buffer
MOVWF
TRISC
RD TRIS
Q D EN EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 5-5:
Name RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7
PORTC FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output
Legend: ST = Schmitt Trigger input
TABLE 5-6:
Address Name 07h 87h PORTC TRISC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 RC7 TRISC7 Bit 6 RC6 TRISC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on: POR, BOR xxxx xxxx Value on all other resets uuuu uuuu 1111 1111
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
Legend: x = unknown, u = unchanged.
DS30559A-page 34
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
5.4 PORTD and TRISD Registers (PIC16C661 and PIC16C662 only) FIGURE 5-8:
Data bus WR PORT
PORTD BLOCK DIAGRAM (IN I/O PORT MODE)
D Q
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
I/O pin(1)
CK
Data Latch
D Q
WR TRIS
CK
TRIS Latch
Schmitt Trigger input buffer
RD TRIS
Q D EN EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 5-7:
Name RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6
PORTD FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL ST/TTL
(1) (1)
Function Input/output port pin or parallel slave port bit0 Input/output port pin or parallel slave port bit1 Input/output port pin or parallel slave port bit2 Input/output port pin or parallel slave port bit3 Input/output port pin or parallel slave port bit4 Input/output port pin or parallel slave port bit5 Input/output port pin or parallel slave port bit6
ST/TTL(1) ST/TTL ST/TTL
(1) (1)
RD7/PSP7 bit7 Input/output port pin or parallel slave port bit7 Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
ST/TTL(1)
TABLE 5-8:
Address Name 08h 88h 89h PORTD TRISD TRISE
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7 RD7 Bit 6 RD6 Bit 5 RD5 Bit 4 RD4 TRISD4 PSPMODE Bit 3 RD3 Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on: POR, BOR xxxx xxxx Value on all other resets uuuu uuuu 1111 1111 0000 -111
TRISD7 TRISD6 TRISD5 IBF OBF IBOV
TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 -- TRISE2 TRISE1 TRISE0 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 35
PIC16C64X & PIC16C66X
5.5 PORTE and TRISE Register (PIC16C661 and PIC16C662 only)
Figure 5-9 shows the TRISE register, which also controls the parallel slave port operation. PORTE has three pins RE0/RD, RE1/WR, and RE2/ CS, which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs). In this mode the input buffers are TTL.
FIGURE 5-9:
R-0 IBF bit7
TRISE REGISTER (ADDRESS 89h)
R/W-0 IBOV R/W-0 PSPMODE U-0 -- R/W-1 TRISE2 R/W-1 TRISE1 R/W-1 TRISE0 bit0
R-0 OBF
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel slave port mode 0 = General purpose I/O mode Unimplemented: Read as '0' TRISE2: Direction control bit for pin RE2/CS 1 = Input 0 = Output TRISE1: Direction control bit for pin RE1/WR 1 = Input 0 = Output TRISE0: Direction control bit for pin RE0/RD 1 = Input 0 = Output
bit 6:
bit 5:
bit 4:
bit 3: bit 2:
bit 1:
bit 0:
DS30559A-page 36
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 5-10: PORTE BLOCK DIAGRAM (IN I/O PORT MODE)
Data Bus WR PORT
D Q
I/O pin
CK Q
Data Latch
D
Q Q
WR TRIS
CK
TRIS Latch
Schmitt Trigger input buffer
RD TRIS
Q
D EN EN
RD PORT Note: I/O pins have protection diodes to VDD and VSS.
TABLE 5-9:
Name RE0/RD
PORTE FUNCTIONS
Bit# bit0 Buffer Type ST/TTL(1) Function Input/output port pin or read control input in parallel slave port mode: RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected) Input/output port pin or write control input in parallel slave port mode: WR 1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected)
RE1/WR
bit1
ST/TTL(1)
Input/output port pin or chip select control input in parallel slave port mode: CS 1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode. RE2/CS
bit2
ST/TTL(1)
TABLE 5-10:
Address 09h 89h Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7 -- IBF Bit 6 -- OBF Bit 5 -- IBOV Bit 4 -- PSPMODE Bit 3 -- -- Bit 2 RE2 TRISE2 Bit 1 RE1 TRISE1 Bit 0 RE0 TRISE0 Value on: POR, BOR ---- -xxx 0000 -111 Value on all other resets ---- -uuu 0000 -111
PORTE TRISE
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 37
PIC16C64X & PIC16C66X
5.6
5.6.1
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-4:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. Reading the port register reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (e.g., BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. Example 5-4 shows the effect of two sequential read-modify-write instructions on an I/O port. A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip.
;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- --------BCF PORTB, 7 ; 01pp pppp 11pp pppp BCF PORTB, 6 ; 10pp pppp 11pp pppp BCF STATUS, RP1 ; BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp pppp 11pp pppp BCF TRISB, 6 ; 10pp pppp 10pp pppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high).
5.6.2
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-11). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with an NOP or another instruction not accessing this I/O port.
FIGURE 5-11: SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched PC PC + 1 PC + 2 NOP PC + 3 NOP
Note: This example shows a write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25TCY - TPD)
MOVWF PORTB MOVF PORTB,W write to PORTB
RB7:RB0 Port pin sampled here Instruction executed MOVWF PORTB write to PORTB TPD NOP MOVF PORTB,W
where TCY = instruction cycle TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic.
DS30559A-page 38
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
5.7 Parallel Slave Port (PIC16C661 and PIC16C662 only)
PORTD operates as an 8-bit wide parallel slave port, or as a microprocessor port when control bit PSPMODE (TRISE<4>) is set. In slave mode it is asynchronously readable and writable by the external world through RD control input pin (RE0/RD) and WR control input pin (RE1/WR). It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). There are actually two 8-bit latches, one for data-out (from the PIC16/17) and one for data input. The user writes 8-bit data to PORTD data latch and reads data from the port pin latch (note that they have the same address). In this mode, the TRISD register is ignored since the microprocessor is controlling the direction of data flow. Input Buffer Full Status Flag bit IBF (TRISE<7>) is set if a received word is waiting to be read by the CPU. Once the PORTD input latch is read, bit IBF is cleared. IBF is a read only status bit. Output Buffer Full Status Flag bit OBF (TRISE<6>) is set if a word written to PORTD latch is waiting to be read by the external bus. Once the PORTD output latch is read by the microprocessor, bit OBF is cleared. Input Buffer Overflow Status flag bit IBOV (TRISE<5>) is set if a second write to the microprocessor port is attempted when the previous word has not been read by the CPU (the first word is retained in the buffer). When not in Parallel Slave Port mode, bits IBF and OBF are held clear. However, if flag bit IBOV was previously set, it must be cleared in software. An interrupt is generated and latched into flag bit PSPIF (PIR1<7>) when a read or a write operation is completed. Flag bit PSPIF must be cleared by user software. The interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>).
FIGURE 5-12: PORTD AND PORTE AS A PARALLEL SLAVE PORT
Data bus
D Q
WR PORT
CK
RDx pin TTL
Q
D EN EN
RD PORT One bit of PORTD
Set interrupt flag PSPIF (PIR1<7>)
Read
TTL
RD CS WR
Chip Select
TTL
Write
TTL
Note: I/O pins have protection diodes to VDD and VSS.
TABLE 5-11:
Address 08h 09h 89h 0Ch 8Ch Name PORTD PORTE TRISE PIR1 PIE1
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Bit 7 PSP7 -- IBF PSPIF(1) PSPIE(1) Bit 6 PSP6 -- OBF CMIF CMIE Bit 5 PSP5 -- IBOV -- -- Bit 4 PSP4 -- PSPMODE -- -- Bit 3 PSP3 -- -- -- -- Bit 2 PSP2 RE2 Bit 1 PSP1 RE1 Bit 0 PSP0 RE0 Value on: POR, BOR xxxx xxxx ---- -xxx 0000 -111 00-- ---00-- ---Value on all other resets uuuu uuuu ---- -uuu 0000 -111 00-- ---00-- ----
TRISE2 TRISE1 TRISE0 -- -- -- -- -- --
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by the PSP. Note 1: These bits are reserved on the PIC16C641/642, always maintain these bits clear.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 39
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 40
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
6.0 TIMER0 MODULE
The Timer0 module has the following features: * 8-bit timer/counter register, TMR0 - Read and write capability - Interrupt on overflow from FFh to 00h * 8-bit software programmable prescaler * Internal or external clock select - Edge select for external clock Figure 6-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing bit T0CS (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS. In this mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Section 6.3 details the operation of the prescaler.
6.1
Timer0 Interrupt
The TMR0 interrupt is generated when the register (TMR0) overflows from FFh to 00h. This overflow sets interrupt flag bit T0IF (INTCON<2>). The interrupt can be masked by clearing enable bit T0IE (INTCON<5>). Flag bit T0IF must be cleared in software by the Timer0 interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP. Figure 6-4 displays the Timer0 interrupt timing.
FIGURE 6-1:
RA4/T0CKI pin
TIMER0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 Programmable Prescaler 0 PSout Sync with Internal clocks (2 cycle delay) Set bit T0IF on overflow 8 TMR0 reg PSout
T0SE 3 PS2, PS1, PS0 T0CS PSA
Note 1: Bits, T0CS, T0SE, PSA, and PS2, PS1, PS0 are (OPTION<5:0). 2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed diagram).
FIGURE 6-2:
PC (Program Counter) Instruction Fetch
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 PC+2 PC+3 PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
TMR0 Instruction Executed
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
Read TMR0 reads NT0 + 2
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 41
PIC16C64X & PIC16C66X
FIGURE 6-3:
PC (Program Counter) Instruction Fetch TMR0 T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 PC+2 PC+3 PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+1
NT0
NT0+1
T0
Instruction Execute
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
FIGURE 6-4:
TIMER0 INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 CLKOUT(3) Timer0 T0IF bit (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC +1 Inst (PC+1) Dummy cycle PC +1 0004h Inst (0004h) Dummy cycle 0005h Inst (0005h) Inst (0004h) FEh 1 FFh 1 00h 01h 02h
Inst (PC)
Note 1: Interrupt flag bit T0IF is sampled here (every Q1). 2: Interrupt latency = 4Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode.
DS30559A-page 42
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
6.2 Using Timer0 with External Clock
When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 6.2.1 EXTERNAL CLOCK SYNCHRONIZATION When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41, and 42 in the electrical specification of the desired device. 6.2.2 TIMER0 INCREMENT DELAY
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.
FIGURE 6-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock Input or Prescaler output (2)
(1) (3)
External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 43
PIC16C64X & PIC16C66X
6.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (Figure 6-6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x) will clear the prescaler count. When assigned to Watchdog Timer, a CLRWDT instruction will clear the prescaler count along with the Watchdog Timer. The prescaler is not readable or writable.
FIGURE 6-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (=Fosc/4)
0 RA4/T0CKI pin 1 T0SE
M U X
T0CS
PSA
Set flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
DS30559A-page 44
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
6.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control, i.e., it can be changed "on the fly" during program execution. Note: To avoid an unintended device RESET, the following instruction sequence (shown in Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This precaution must be followed even if the WDT is disabled. To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2.
EXAMPLE 6-2:
CLRWDT BSF MOVLW MOVWF BCF
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ;prescaler STATUS, RP0 ;Bank 1 b'xxxx0xxx' ;Select TMR0, new ;prescale value and OPTION_REG ;clock source STATUS, RP0 ;Bank 0
EXAMPLE 6-1:
BCF CLRF BSF CLRWDT MOVLW MOVWF BCF
CHANGING PRESCALER (TIMER0WDT)
;Bank 0 ;Clear TMR0 & Prescaler ;Bank 1 ;Clears WDT ;Select new prescale ;value & WDT ;Bank 0
STATUS, RP0 TMR0 STATUS, RP0 b'xxxx1xxx' OPTION_REG STATUS, RP0
TABLE 6-1:
Address Name 01h 0Bh/8Bh 81h 85h TMR0
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR xxxx xxxx INTE T0SE RBIE PSA T0IF PS2 INTF PS1 RBIF PS0 0000 000x 1111 1111 Value on all other resets uuuu uuuu 0000 000u 1111 1111 --11 1111
Timer0 module's register GIE PEIE T0IE T0CS TRISA5
INTCON OPTION TRISA
RBPU INTEDG -- --
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 45
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 46
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
7.0 COMPARATOR MODULE
The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with pins RA0 through RA4. The on-chip Voltage Reference (Section 8.0) can also be an input to the comparators. The CMCON register, shown in Figure 7-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 7-2.
FIGURE 7-1:
R-0 C2OUT bit7
CMCON REGISTER (ADDRESS 1Fh)
U-0 -- U-0 -- R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit0
R-0 C1OUT
R =Readable bit W =Writable bit U =Unimplemented bit, read as `0' - n =Value at POR reset
bit 7:
C2OUT: Comparator 2 output 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- C1OUT: Comparator 1 output 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- CIS: Comparator Input Switch When CM2:CM0: = 001: Then: 1 = C1 VIN- connects to RA3 0 = C1 VIN- connects to RA0 When CM2:CM0 = 010: Then: 1 = C1 VIN- connects to RA3 C2 VIN- connects to RA2 0 = C1 VIN- connects to RA0 C2 VIN- connects to RA1
bit 6:
bit 5-4: Unimplemented: Read as '0' bit 3:
bit 2-0: CM2:CM0: Comparator mode Figure 7-2 shows the comparator modes and CM2:CM0 bit settings.
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 47
PIC16C64X & PIC16C66X
7.1 Comparator Configuration
There are eight modes of operation for the comparators. The CMCON register is used to select the mode. Figure 7-2 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Table 12-2. Note: Comparator interrupts should be disabled during a comparator mode change otherwise a false interrupt may occur.
FIGURE 7-2:
COMPARATOR I/O OPERATING MODES
Comparators Off CM2:CM0 = 111 RA0/AN0 C1 Off (Read as '0') RA3/AN3
D D VINVIN+
Comparators Reset (POR Default Value) CM2:CM0 = 000 RA0/AN0 RA3/AN3
A A VINVIN+
C1
Off (Read as '0')
RA1/AN1 RA2/AN2
A A
VINVIN+
RA1/AN1 C2 Off (Read as '0') RA2/AN2
D D
VINVIN+
C2
Off (Read as '0')
Two Independent Comparators CM2:CM0 = 100 RA0/AN0 RA3/AN3
A A VINVIN+
Four Inputs Multiplexed to Two Comparators CM2:CM0 = 010 RA0/AN0
A A CIS = 0 CIS = 1 VINVIN+ A A CIS = 0 CIS = 1 VINVIN+
C1
C1OUT
RA3/AN3 RA1/AN1
C1
C1OUT
RA1/AN1 RA2/AN2
A A
VINVIN+
C2
C2OUT
RA2/AN2
C2
C2OUT
From VREF Module Two Common Reference Comparators CM2:CM0 = 011 RA0/AN0 RA3/AN3
A D VINVIN+
Two Common Reference Comparators with Outputs CM2:CM0 = 110 RA0/AN0
A D VINVIN+
C1
C1OUT
RA3/AN3
C1
C1OUT
RA1/AN1 RA2/AN2
A A
VINVIN+
RA1/AN1 C2 C2OUT RA2/AN2
A A
VINVIN+
C2
C2OUT
RA4 Open Drain
One Independent Comparator CM2:CM0 = 101 RA0/AN0 RA3/AN3
D D VINVIN+
Three Inputs Multiplexed to Two Comparators CM2:CM0 = 001 RA0/AN0
A A CIS = 0 CIS = 1 VINVIN+
C1
Off (Read as '0')
RA3/AN3
C1
C1OUT
RA1/AN1 RA2/AN2
A A
VINVIN+
RA1/AN1 C2 C2OUT RA2/AN2
A A
VINVIN+
C2
C2OUT
A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch.
DS30559A-page 48
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
The code example in Example 7-1 depicts the steps required to configure the comparator module. RA3 and RA4 are configured as digital outputs. RA0 and RA1 are configured as the V- inputs and RA2 as the V+ input to both comparators.
7.3
Comparator Reference
EXAMPLE 7-1:
FLAG_REG CLRF CLRF ANDLW IORWF MOVLW MOVWF BSF MOVLW MOVWF
INITIALIZING THE COMPARATOR MODULE
;Init Flag Register ;Init PORTA ;Mask Comp bits ;Bits to Flag_Reg ;Init Comp Mode ;CM2:CM0 = 011 ;Select Bank 1 ;Init Data direction ;RA<2:0> to inputs ;RA<4:3> to outputs ;TRISA<7:5> read '0' ;Select Bank 0 ;10 s delay ;Read CMCON to end ;change condition ;Clear Pending Ints ;Select Bank 1 ;Enable Comp Ints ;Select Bank 0 ;Enable Periph Ints ;Global Int enable
An external or internal reference signal may be used depending on the comparator operating mode. The analog signal that is present at VIN- is compared to the signal at VIN+, and the digital output of the comparator is adjusted accordingly (Figure 7-3).
EQU 0x20 FLAG_REG PORTA 0xC0 FLAG_REG,F 0x03 CMCON STATUS,RP0 0x07 TRISA
FIGURE 7-3:
VINVIN+
SINGLE COMPARATOR
Output
BCF CALL MOVF BCF BSF BSF BCF BSF BSF
STATUS,RP0 DELAY_10s CMCON,F PIR1,CMIF STATUS,RP0 PIE1,CMIE STATUS,RP0 INTCON,PEIE INTCON,GIE
VINVIN+
Output
7.3.1
EXTERNAL REFERENCE SIGNAL
7.2
Comparator Operation
A single comparator is shown in Figure 7-3 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 7-3 represents the uncertainty due to input offsets and response time.
When external voltage references are used, the comparator module can be configured to have the comparators operate from the same or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD, and can be applied to either pin of the comparator(s). 7.3.2 INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an internally generated voltage reference for the comparators. Section 8.0, contains a detailed description of the Voltage Reference Module that provides this signal. The internal reference signal is used when the comparators are in mode CM2:CM0 = 010 (Figure 7-2). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 49
PIC16C64X & PIC16C66X
7.4 Comparator Response Time 7.5 Comparator Outputs
Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is guaranteed to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (Table 12-2 and Table 12-3). The comparator outputs are read through the CMCON register. These bits are read only. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. When CM2:CM0 = 110, multiplexors in the output path of the RA3 and RA4 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 7-4 shows the comparator output block diagram. The TRISA bits will still function as an output enable/ disable for the RA3 and RA4 pins while in this mode. Note 1: When reading the PORTA register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. Note 2: Analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified.
FIGURE 7-4:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins MULTIPLEX
To RA3 or RA4 pin To Data Bus Q D EN RD CMCON
Set CMIF bit
Q
D EN CL RD CMCON
From other Comparator
NRESET
DS30559A-page 50
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
7.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is a change in the output value of either comparator. User software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that has occurred. The CMIF bit (PIR1<6>), is the comparator interrupt flag and must be cleared in user software. To enable the Comparator interrupt the following bits must be set: * CMIE (PIE1<6>) * PEIE (INTCON<6>) * GIE (INTCON<7>) The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON. This will end the mismatch condition. Clear flag bit CMIF. comparators, CM2:CM0 = 111, before entering sleep. If the device wakes up from sleep, the contents of the CMCON register are not affected.
7.8
Effects of a RESET
A device reset forces the CMCON register to its reset state. This forces the comparator module to be in the comparator reset mode, CM2:CM0 = 000. This ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at reset time. The comparators will be powered down during the reset interval.
7.9
Analog Input Connection Considerations
A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition, and allow flag bit CMIF to be cleared.
7.7
Comparator Operation During SLEEP
When a comparator is active and the device is placed in SLEEP mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake up the device from SLEEP mode when enabled. While the comparator is powered up, higher sleep currents than shown in the power-down current specification will occur. Each comparator that is operational will consume additional current as shown in the comparator specifications. To minimize power consumption while in SLEEP mode, turn off the
A simplified circuit for an analog input is shown in Figure 7-5. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.
FIGURE 7-5:
ANALOG INPUT MODEL
VDD RS AIN VT = 0.6V RC < 10k
VA
CPIN 5 pF
VT = 0.6V
ILEAKAGE 500 nA
VSS Legend CPIN VT ILEAKAGE RIC RS VA = Input Capacitance = Threshold Voltage = Leakage Current at the pin due to various junctions = Interconnect Resistance = Source Impedance = Analog Voltage
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 51
PIC16C64X & PIC16C66X
TABLE 7-1:
Address Name 1Fh 9Fh 0Bh/8Bh 0Ch 8Ch 85h CMCON VRCON INTCON PIR1 PIE1 TRISA
REGISTERS ASSOCIATED WITH THE COMPARATOR MODULE
Bit 7 C2OUT VREN GIE PSPIF(1) PSPIE(1) -- Bit 6 C1OUT VROE PEIE CMIF CMIE -- Bit 5 -- VRR T0IE -- -- Bit 4 -- -- INTE -- -- Bit 3 CIS VR3 RBIE -- -- Bit 2 CM2 VR2 T0IF -- -- Bit 1 CM1 VR1 INTF -- -- Bit 0 CM0 VR0 RBIF -- -- Value on POR, BOR 00-- 0000 000- 0000 0000 000x 00-- ---00-- ---Value on all other resets 00-- 0000 000- 0000 0000 000u 00-- ---00-- -----11 1111
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111
Note 1: These bits are reserved on the PIC16C641/642, always maintain these bits clear.
DS30559A-page 52
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
8.0 VOLTAGE REFERENCE MODULE
The VRCON register, shown in Figure 8-1, controls the operation of the Voltage Reference Module. The block diagram is given in Figure 8-2.
The Voltage Reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of VREF values and has a power-down function to conserve power when the reference module is not being used.
FIGURE 8-1:
R/W-0 VREN bit7
VRCON REGISTER (ADDRESS 9Fh)
R/W-0 VRR U-0 -- R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit0
R/W-0 VROE
R =Readable bit W =Writable bit U =Unimplemented bit, read as `0' - n =Value at POR reset
bit 7:
VREN: VREF Enable 1 = VREF circuit powered up 0 = VREF circuit powered down, no IDD drain VROE: VREF Output Enable 1 = VREF is output on RA2 pin 0 = VREF is disconnected from RA2 pin VRR: VREF Range selection 1 = Low Range 0 = High Range Unimplemented: Read as '0' When: VRR = 1 Then: VREF = (VR3:VR0/ 24) * VDD When: VRR = 0 Then: VREF = 1/4 * VDD + (VR3:VR0/ 32) * VDD
bit 6:
bit 5:
bit 4:
bit 3-0: VR3:VR0: VREF value selection 0 VR3:VR0 15
FIGURE 8-2:
VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VREN
8R
R
R
R
R
8R
VRR
VREF
16-1 Analog Mux
VR3 VR2 (From VRCON<3:0>) VR1 VR0
Note:
R is defined in Table 12-3.
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 53
PIC16C64X & PIC16C66X
8.1 Configuring the Voltage Reference
The Voltage Reference Module can output 16 distinct voltage levels for each range. The equations used to calculate the output of the Voltage Reference are as follows: If VRR = 1 Then VREF = (VR3:VR0/24) * VDD If VRR = 0 Then VREF = (VDD * 1/4) + (VR3:VR0/32) * VDD The settling time of the Voltage Reference must be considered when changing the VREF output (Table 12-2). Example 8-1 shows an example of how to configure the Voltage Reference for an output voltage of 1.25V with VDD = 5.0V. the VREF output changes with fluctuations in VDD. The absolute accuracy of the Voltage Reference can be found in Table 12-3.
8.3
Operation During Sleep
When the device wakes up from sleep through an interrupt or a Watchdog Timer time-out, the contents of the VRCON register are not affected. To minimize current consumption in SLEEP mode, the Voltage Reference Module should be disabled.
8.4
Effects of a Reset
EXAMPLE 8-1:
MOVLW MOVWF BSF MOVLW MOVWF MOVLW MOVWF BCF CALL
VOLTAGE REFERENCE CONFIGURATION
; ; ; ; ; ; ; ; 4 inputs muxed to 2 comparators Select Bank 1 RA3:RA0 to outputs enable Vref low range, VR3:VR0 = 6 Select Bank 0 ; 10 s delay
A device reset disables the Voltage Reference by clearing bit VREN (VRCON<7>). This reset also disconnects the reference from the RA2 pin by clearing bit VROE (VRCON<6>) and selects the high voltage range by clearing bit VRR (VRCON<5>). The VREF value select bits, VRCON<3:0>, are also cleared.
0x02 CMCON STATUS,RP0 0x07 TRISA 0xA6 VRCON STATUS,RP0 DELAY_10s
8.5
Connection Considerations
8.2
Voltage Reference Accuracy/Error
The Voltage Reference Module operates independently of the comparator module. The output of the reference generator may be connected to the RA2 pin if the TRISA<2> bit is set and bit VROE is set. Enabling the Voltage Reference output onto the RA2 pin with an input signal present will increase current consumption. Connecting RA2 as a digital output with VREF enabled will also increase current consumption. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited drive capability, a buffer must be used in conjunction with the Voltage Reference output for external connections to VREF. Figure 8-3 shows an example buffering technique.
The full range of VSS to VDD cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 8-2) keep VREF from approaching VSS or VDD. The Voltage Reference is VDD derived and therefore,
FIGURE 8-3:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC16C662 R(1) Voltage Reference Output Impedance Pin RA2 VREF output
VREF Module
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
TABLE 8-1:
Address Name 9Fh 1Fh 85h VRCON
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Bit 7 VREN C2OUT -- Bit 6 VROE C1OUT -- Bit 5 VRR -- Bit 4 -- -- Bit 3 VR3 CIS Bit 2 VR2 CM2 Bit 1 VR1 CM1 Bit 0 VR0 CM0 Value On POR, BOR 000- 0000 00-- 0000 --11 1111 Value on all other resets 000- 0000 00-- 0000 --11 1111
CMCON TRISA
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
DS30559A-page 54
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.0 SPECIAL FEATURES OF THE CPU
The PIC16C64X & PIC16C66X has a Watchdog Timer which is enabled by a configuration bit (WDTE). It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. Circuitry has been provided for checking program memory parity with a reset when an error is indicated. There is also circuitry to reset the device if a brown-out occurs which provides at least a 72 ms reset. With these three functions on-chip, most applications need no external reset circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.
What sets apart a microcontroller from other processors are special circuits to deal with the needs of real-time applications. The PIC16C64X & PIC16C66X families have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: 1. 2. Oscillator selection Resets Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Brown-out Reset (BOR) Parity Error Reset (PER) Interrupts Watchdog Timer (WDT) SLEEP Code protection ID Locations In-circuit serial programming
3. 4. 5. 6. 7. 8.
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 55
PIC16C64X & PIC16C66X
9.1 Configuration Bits
The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h-3FFFh), which can be accessed only during programming.
FIGURE 9-1:
CP1 bit13 bit 13-8 5-4: CP0 CP1
CONFIGURATION WORD
CP0 CP1 CP0 MPEEN BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 bit0 CONFIG REGISTER: Address 2007h
CP1:CP0: Code protection bits(2)
11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected MPEEN: Memory Parity Error Enable 1 = Memory Parity Checking is enabled 0 = Memory Parity Checking is disabled BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
bit 7:
bit 6:
bit 3:
bit 2:
bit 1-0:
Note
DS30559A-page 56
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.2
9.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 9-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS (PRELIMINARY)
Ranges tested:
The PIC16CXXX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR / CERAMIC RESONATORS
Mode XT
Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz
OSC1 22 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
HS
9.2.2
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 9-2). The PIC16CXXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1 pin (Figure 9-3).
Note: Recommended values of C1 and C2 are identical to the ranges tested table. Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
Resonators used: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX 0.3% 0.5% 0.5% 0.5% 0.5%
FIGURE 9-2:
CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)
OSC1
All resonators used did not have built-in capacitors.
TABLE 9-2:
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR (PRELIMINARY)
Freq OSC1 68 - 100 pF 15 - 30 pF 68 - 150 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF OSC2 68 - 100 pF 15 - 30 pF 150 - 200 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF 15 - 30 pF
C1 XTAL OSC2 C2 RS see Note RF
To internal logic
Mode
SLEEP
LP XT
PIC16CXXX
See Table 9-1 or Table 9-2 for recommended values of C1 and C2. Note: A series resistor may be required for AT strip cut crystals.
HS
32 kHz 200 kHz 100 kHz 2 MHz 4 MHz 8 MHz 10 MHz 20 MHz
FIGURE 9-3:
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
clock from ext. system Open
Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
OSC1 PIC16CXXX OSC2
Crystals used: 32.768 kHz 100 kHz 200 kHz 2.0 MHz 4.0 MHz 10.0 MHz 20.0 MHz Epson C-001R32.768K-A Epson C-2 100.00 KC-P STD XTL 200.000 kHz ECS ECS-20-S-2 ECS ECS-40-S-4 ECS ECS-100-S-4 ECS ECS-200-S-4 20 PPM 20 PPM 20 PPM 50 PPM 50 PPM 50 PPM 50 PPM
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 57
PIC16C64X & PIC16C66X
9.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 9.2.4 RC OSCILLATOR For timing insensitive applications the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 9-6 shows how the R/C combination is connected to the PIC16CXXX. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g. 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 3 k and 100 k. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. See characterization data for desired device for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). See characterization data for desired device for variation of oscillator frequency due to VDD for given Rext/ Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-3 for waveform).
Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance. Figure 9-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometer biases the 74AS04 in the linear region. This could be used for external oscillator designs.
FIGURE 9-4:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
To Other Devices
+5V 10k 4.7k 74AS04 74AS04 PIC16CXXX CLKIN
10k XTAL 10k 20 pF 20 pF
Figure 9-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180-degree phase shift in a series resonant oscillator circuit. The 330 k resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 9-6:
VDD Rext
RC OSCILLATOR MODE
FIGURE 9-5:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT
To Other Devices 74AS04 PIC16CXXX CLKIN
OSC1
330 k 74AS04 0.1 F XTAL 330 k 74AS04
Internal clock PIC16CXXX
Cext VSS Fosc/4 OSC2/CLKOUT
DS30559A-page 58
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.3 Reset
The PIC16CXXX differentiates between various kinds of reset: a) b) c) d) e) f) Power-on reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT reset (normal operation) Brown-out Reset (BOR) Parity Error Reset (PER) state" on Power-on reset, MCLR, WDT reset, Brown-out Reset, Parity Error Reset, and on MCLR reset during SLEEP. They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different reset situations as indicated in Table 9-4. These bits are used in software to determine the nature of the reset. See Table 9-6 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 9-7. The MCLR reset path has a noise filter to detect and ignore small pulses. See Table 12-6 for pulse width specification.
Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset
FIGURE 9-7:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR/ VPP Pin Program Memory Parity MPEEN
WDT SLEEP Module WDT Time-out VDD rise detect VDD Brown-out Reset OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN Pin On-chip(1) RC OSC R Q Chip_Reset BODEN S Power-on Reset
PWRT 10-bit Ripple-counter
Enable PWRT Enable OST
See Table 9-3 for time-out situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 59
PIC16C64X & PIC16C66X
9.4 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST), Brown-out Reset (BOR), and Parity Error Reset (PER)
POWER-ON RESET (POR) The power-up time delay will vary from chip to chip due to VDD, temperature, and process variations. See DC parameters for details. 9.4.3 OSCILLATOR START-UP TIMER (OST)
9.4.1
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.6V to 1.8V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is required. See Electrical Specifications for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For additional information, refer to Application Note AN607 "Power-up Trouble Shooting." 9.4.2 POWER-UP TIMER (PWRT)
The Oscillator Start-Up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, and HS modes and only on Power-on Reset or wake-up from SLEEP. 9.4.4 BROWN-OUT RESET (BOR)
The Power-up Timer provides a fixed 72 ms (nominal) delay on power-up only, from POR or BOR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as PWRT is active. The PWRT delay allows VDD to rise to an acceptable level. A configuration bit, PWRTE can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should always be enabled when Brown-out Reset is enabled.
PIC16C64X & PIC16C66X devices have on-chip Brown-out Reset circuitry. A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below 4.0V (Parameter D005 in ES section) for greater than parameter 35 in Table 12-6, the brown-out situation will reset the chip. A reset is not guaranteed to occur if VDD falls below 4.0V for less than parameter 35. The chip will remain in Brown-out Reset until VDD rises above BVDD. The Power-up Timer will now be invoked and will keep the chip in reset an additional 72 ms. If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer will execute a 72 ms time delay. The Power-up Timer should always be enabled when Brown-out Reset is enabled. Figure 9-8 shows typical Brown-out situations.
FIGURE 9-8:
BROWN-OUT SITUATIONS
VDD BVDD Max. BVDD Min. 72 ms
Internal Reset VDD
BVDD Max. BVDD Min. <72 ms 72 ms
Internal Reset
VDD
BVDD Max. BVDD Min. 72 ms
Internal Reset
DS30559A-page 60
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.4.5 PARITY ERROR RESET (PER) 9.4.7 PIC16C64X & PIC16C66X devices have on-chip parity bits that can be used to verify the contents of program memory. Parity bits may be useful in applications in order to increase overall reliability of a system. There are two parity bits for each word of Program Memory. The parity bits are computed on alternating bits of the program word. One computation is performed using even parity, the other using odd parity. As a program executes, the parity is verified. The even parity bit is XOR'd with the even bits in the program memory word. The odd parity bit is negated and XOR'd with the odd bits in the program memory word. When an error is detected, a reset is generated and the PER flag bit in the PCON register is set. This indication can allow software to act on a failure. However, there is no indication of the program memory location of the failure of the Program Memory. This flag can only be cleared in software or by a POR. The parity array is user selectable during programming. Bit7 of the configuration word located at address 2007h can be programmed (read as '0') to disable parity checking. If left unprogrammed (read as '1'), parity checking is enabled. 9.4.6 TIME-OUT SEQUENCE POWER CONTROL/STATUS REGISTER (PCON)
The power control/status register, PCON (address 8Eh) has four bits. See Figure 4-10 for register. Bit0 is BOR (Brown-out Reset). BOR is unknown on a Power-on-reset. It must initially be set by the user and checked on subsequent resets to see if BOR = '0' indicating that a Brown-out Reset has occurred. The BOR status bit is a "don't care" bit and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Configuration word). Bit1 is POR (Power-on Reset). It is cleared on a Power-on Reset and is unaffected otherwise. The user set this bit following a Power-on Reset. On subsequent resets if POR is `0', it will indicate that a Power-on Reset must have occurred. Bit2 is PER (Parity Error Reset). It is cleared on a Parity Error Reset and must be set by user software. It will also be set on a Power-on Reset. Bit7 is MPEEN (Memory Parity Error Enable). This bit reflects the status of the MPEEN bit in configuration word. It is unaffected by any reset or interrupt.
On power-up, the time-out sequence is as follows: First PWRT time-out is invoked after POR has expired. Then the OST is activated. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in RC mode with the PWRTE bit set (PWRT disabled), there will be no time-out at all. Figure 9-9, Figure 9-10 and Figure 9-11 depict time-out sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure 9-10). This is useful for testing purposes or to synchronize more than one device operating in parallel. Table 9-5 shows the reset conditions for some special registers, while Table 9-6 shows the reset conditions for all the registers.
TABLE 9-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Oscillator Configuration PWRTE = 0 XT, HS, LP RC 72 ms + 1024 TOSC 72 ms PWRTE = 1 1024 TOSC --
Brown-out Reset
Wake-up from SLEEP 1024 TOSC --
72 ms + 1024 TOSC 72 ms
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 61
PIC16C64X & PIC16C66X
TABLE 9-4:
PER 1 x x 1 1 1 1 1 0 0 0
STATUS BITS AND THEIR SIGNIFICANCE
POR 0 0 0 1 1 1 1 1 1 0 x BOR x x x 0 1 1 1 1 1 x 0 TO 1 0 x 1 0 0 u 1 1 x x PD 1 x 0 1 1 0 u 0 1 x x Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR reset during normal operation MCLR reset during SLEEP Parity Error Reset Illegal, PER is set on POR Illegal, PER is set on BOR
TABLE 9-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program Counter 000h 000h 000h 000h PC + 1 000h 000h PC + 1(1) STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu 0001 1uuu uuu1 0uuu PCON Register u--- -10x u--- -uuu u--- -uuu u--- -uuu u--- -uuu u--- -uu0 1--- -0uu u--- -uuu
Condition Power-on Reset MCLR reset during normal operation MCLR reset during SLEEP WDT reset WDT Wake-up Brown-out Reset Parity Error Reset Interrupt Wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1.
DS30559A-page 62
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
TABLE 9-6: INITIALIZATION CONDITION FOR REGISTERS
Power-on Reset Brown-out Reset Parity Error Reset xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --xx 0000 xxxx xxxx xxxx xxxx xxxx xxxx ---- -xxx 00-- 0000 ---0 0000 0000 000x 00-- ---1111 1111 --11 1111 1111 1111 1111 1111 1111 1111 0000 -111 00-- ---u--- -qqq 000- 0000 MCLR Reset during: - normal operation - SLEEP or WDT Reset uuuu uuuu uuuu uuuu 0000 0000 000q quuu(3) uuuu uuuu --xu 0000 uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu 00-- 0000 ---0 0000 0000 000u 00-- ---1111 1111 --11 1111 1111 1111 1111 1111 1111 1111 0000 -111 00-- ---u--- -uuu 000- 0000 Wake up from SLEEP through: - interrupt - WDT time-out uuuu uuuu uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu uu-- uuuu ---u uuuu uuuu uuuu(1) uu-- ----(1) uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uu-- ---u--- -uuu uuu- uuuu
Register
Address
W INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(4) PORTE(4) CMCON PCLATH INTCON PIR1 OPTION TRISA TRISB TRISC TRISD
(4)
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 1Fh 0Ah 0Bh 0Ch 81h 85h 86h 87h 88h 89h 8Ch 8Eh 9Fh
TRISE(4) PIE1 PCON VRCON
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0',q = value depends on condition. Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 9-5 for reset value for specific condition. 4: These registers are associated with the Parallel Slave Port and are not implemented on the PIC16C641/642.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 63
PIC16C64X & PIC16C66X
FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30559A-page 64
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 9-12: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD VDD
FIGURE 9-14: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2
VDD R1 Q1 MCLR VDD
D
R R1 MCLR C R2 40k
PIC16CXXX
PIC16CXXX
Note 1: External power-on reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
Note 1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that:
R1 VDD * R1 + R2 = 0.7 V
2: Internal Brown-out Reset circuitry should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor.
FIGURE 9-13: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1
VDD 33k 10k 40k MCLR PIC16CXXX VDD
Note 1: This circuit will activate reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage. 2: Internal Brown-out Reset circuitry should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 65
PIC16C64X & PIC16C66X
9.5 Interrupts
The PIC16C641 and PIC16C642 have four sources of interrupt, while the PIC16C661 and PIC16C662 have five sources: * * * * * External interrupt RB0/INT TMR0 overflow interrupt PORTB change interrupts (pins RB7:RB4) Comparator interrupt Parallel Slave Port interrupt (PIC16C661/662) When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the RB0/INT or Port RB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 9-16). The latency is the same for one or two cycle instructions. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. Note 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE bit. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again.
The interrupt control register, (INTCON), records individual core interrupt requests in flag bits. It also has various individual enable bits and the global interrupt enable bit. The global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. GIE is cleared on reset. The "return from interrupt" instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which allows any pending interrupt to execute. Those interrupts associated with the "core" have their flag and enable bits in the INTCON register. The core interrupts are: RB0/INT pin interrupt, the RB port change interrupt, and the TMR0 overflow interrupt. The INTCON register also contains the Peripheral Interrupt Enable bit, PEIE. Bit PEIE will enable/mask the peripheral interrupts (CM and PSP) from vectoring when bit PEIE is set/cleared. Flag bits PSPIF and CMIF are contained in special function register PIR1. The corresponding interrupt enable bits (PSPIE and CMIE) are contained in special function register PIE1.
FIGURE 9-15: INTERRUPT LOGIC
T0IF T0IE INTF INTE RBIF RBIE GIE CMIF CMIE PSPIF(1) PSPIE(1) Note 1: The Parallel Slave Port is implemented on the PIC16C661 and PIC16C662 only. PEIE Wake-up (If in SLEEP mode)
Interrupt to CPU
DS30559A-page 66
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.5.1 RB0/INT INTERRUPT 9.5.3 PORTB INTERRUPT The external interrupt on the RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION<6>) is set, or falling, if bit INTEDG is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit INTE (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re-enabling this interrupt. The RB0/INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up. See Section 9.8 for details on SLEEP and Figure 9-19 for timing of wake-up from SLEEP through RB0/INT interrupt. 9.5.2 TMR0 INTERRUPT An input change on any bit of PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). For operation of PORTB (Section 5.2). 9.5.4 COMPARATOR INTERRUPT
See Section 7.6 for complete description of the comparator interrupt.
An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 6.0.
FIGURE 9-16: RB0/INT PIN INTERRUPT TIMING
Q1 OSC1 CLKOUT 3 INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
4 1 5 Interrupt Latency 2
1
PC Inst (PC) Inst (PC-1)
PC+1 Inst (PC+1) Inst (PC)
PC+1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 67
PIC16C64X & PIC16C66X
9.6 Context Saving During Interrupts
Example 9-1: * * * * Stores the W register regardless of current bank Stores the STATUS register in Bank 0 Executes the ISR code Restores the STATUS (and bank select bit register) * Restores the W register During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt e.g. W register and STATUS register. This will have to be implemented in software. Example 9-1 stores and restores the STATUS and W registers. The user register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x70 - 0x7F in Bank 0). The user register, STATUS_TEMP, must be defined in Bank 0.
EXAMPLE 9-1:
SAVING THE STATUS AND W REGISTERS IN RAM
Copy W to a Temporary Register regardless of current bank Swap STATUS nibbles and place into W register Change to Bank 0 regardless of current bank Save STATUS to a Temporary register in Bank 0 Routine) Swap original STATUS register value into W (restores original bank) Restore STATUS register from W register Swap W_Temp nibbles and return value to W_Temp Swap W_Temp to W to restore original W value without affecting STATUS
MOVWF W_TEMP ; SWAPF STATUS,W ; BCF STATUS,RP0 ; MOVWF STATUS_TEMP ; : : (Interrupt Service : SWAPF STATUS_TEMP,W ; MOVWF STATUS ; SWAPF W_TEMP,F ; SWAPF W_TEMP,W ;
DS30559A-page 68
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.7 Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. The block diagram is shown in Figure 9-17. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. This means that the WDT will run, even if the clock on the OSC1 and OSC2 pins has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation, this is known as a WDT wake-up. The WDT can be permanently disabled by clearing configuration bit WDTE (Section 9.1). 9.7.1 WDT PERIOD the WDT, under software control, by writing to the OPTION register. Thus, time-out periods of up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler (if assigned to the WDT) and prevent it from timing out and generating a device RESET. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out (WDT Reset and WDT wake-up). 9.7.2 WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler) it may take several seconds before a WDT time-out occurs. Note: When the prescaler is assigned to the WDT, always execute a CLRWDT instruction before changing the prescale value, otherwise a WDT reset may occur.
The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out period varies with temperature, VDD and process variations from part to part (see DC specs). If longer time-outs are desired, a prescaler with a division ratio of up to 1:128 can be assigned to
FIGURE 9-17: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 7-6) 0 WDT Timer 1 M U X Postscaler 8 8 - to - 1 MUX WDT Enable Bit PSA To TMR0 (Figure 7-6) 0 MUX 1 PSA PS2:PS0
Note: PSA and PS2:PS0 are bits in the OPTION register.
WDT Time-out
FIGURE 9-18: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name Bit 7 Bit 6 BODEN(1) Bit 5 Bit 4 Bit 3 PWRTE(1) PSA Bit 2 WDTE PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0
MPEEN CP1 CP0 2007h Config. bits 81h OPTION RBPU INTEDG T0CS T0SE Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 9-1 for details of the operation of these bits.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 69
PIC16C64X & PIC16C66X
9.8 Power-Down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit in the STATUS register is cleared, the TO bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, all I/O pins should be either at VDD, or VSS, with no external circuitry drawing current from the I/O pin and the comparators and VREF module should be disabled. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). 9.8.1 WAKE-UP FROM SLEEP When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have an NOP after the SLEEP instruction. 9.8.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag set, one of the following events will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as an NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as an NOP. To ensure that the WDT is clear, a CLRWDT instruction should be executed before a SLEEP instruction.
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. Any device reset Watchdog Timer Wake-up (if WDT was enabled) Interrupt from RB0/INT pin, RB Port change, or the Comparator.
The first event will reset the device upon wake-up. However the latter two events will wake the device and then resume program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device reset. The PD bit, which is set on power-up is cleared when SLEEP is invoked. The TO bit is cleared if WDT wake-up occurred.
FIGURE 9-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 2) TOST(2) Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note
1: 2: 3: 4:
XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
DS30559A-page 70
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.9 Code Protection 9.11 In-Circuit Serial Programming
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices. The PIC16CXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a program/verify mode by holding the RB6 and RB7 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X Programming Specifications (Literature #DS30228). A typical in-circuit serial programming connection is shown in Figure 9-20.
9.10
ID Locations
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Only the least significant 4 bits of the ID locations are used.
FIGURE 9-20: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
External Connector Signals +5V 0V VPP CLK Data I/O To Normal Connections PIC16CXX VDD VSS MCLR/VPP RB6 RB7 VDD To Normal Connections
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 71
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 72
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
10.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 10-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 10-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 10-2 lists the instructions recognized by the MPASM assembler. Figure 10-1 shows the three general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16CXX products, do not use the OPTION and TRIS instructions.
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
TABLE 10-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 label Label name Top of Stack Program Counter PCLATH Program Counter High Latch GIE Global Interrupt Enable bit WDT Watchdog Timer/Counter TO Time-out bit PD Power-down bit dest Destination either the W register or the specified register file location [ ] Options ( ) Contents TOS PC
FIGURE 10-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 87 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 0 0 0
0 k (literal)
k = 11-bit immediate value
<>
Assigned to Register bit field In the set of
italics User defined term (font is courier)
The instruction set is highly orthogonal and is grouped into three basic categories:
(c) 1996 Microchip Technology Inc.
DS30559A-page 73
This document was created with FrameMaker 4 0 4
PIC16C64X & PIC16C66X
10.1 Special Function Registers as Source/Destination
The PIC16C64X & PIC16C66X's orthogonal instruction set allows read and write of all file registers, including special function registers. There are some special situations the user should be aware of: 10.1.1 STATUS AS DESTINATION
If an instruction writes to STATUS, the Z, C, and DC bits may be set or cleared as a result of the instruction and overwrite the original data bits written. For example, executing CLRF STATUS will clear register STATUS, and then set the Z bit leaving 0000 0100b in the register. 10.1.2 PCL AS SOURCE OR DESTINATION
Read, write or read-modify-write on PCL may have the following results: Read PC: Write PCL: Read-Modify-Write: PCL dest PCLATH PCH; 8-bit destination value PCL PCL ALU operand PCLATH PCH; 8-bit result PCL
Where PCH = program counter high byte (not an addressable register), PCLATH = Program counter high holding latch, dest = destination, WREG or f. 10.1.3 BIT MANIPULATION
All bit manipulation instructions are done by first reading the entire register, operating on the selected bit and writing the result back (read-modify-write). The user should keep this in mind when operating on special function registers, such as ports.
DS30559A-page 74
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
TABLE 10-2:
Mnemonic, Operands
INSTRUCTION SET
Description Cycles MSb 14-Bit Opcode LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
(c) 1996 Microchip Technology Inc.
DS30559A-page 75
PIC16C64X & PIC16C66X
10.2
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z
11 111x kkkk kkkk The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
ANDLW k Syntax: Operands: Operation: Status Affected: Encoding: Description:
And Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z
11 1001 kkkk kkkk The contents of W register are AND'ed with the eight bit literal 'k'. The result is placed in the W register.
k
Words: Cycles: Example
1 1
ADDLW 0x15 W W = = 0x10 0x25
Words: Cycles: Example
1 1
ANDLW W W 0x5F = = 0xA3 0x03
Before Instruction After Instruction
Before Instruction After Instruction
ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (dest) C, DC, Z
00 0111 dfff ffff Add the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
ANDWF f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (dest) Z
00 0101 dfff ffff AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
Words: Cycles: Example
1 1
ADDWF FSR, 0 W= FSR = 0x17 0xC2 0xD9 0xC2
Words: Cycles: Example
1 1
ANDWF FSR, 1 W= FSR = 0x17 0xC2 0x17 0x02
Before Instruction
Before Instruction
After Instruction
W= FSR =
After Instruction
W= FSR =
DS30559A-page 76
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
BCF FLAG_REG, 7 FLAG_REG = 0xC7
Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None
01 00bb bfff ffff Bit 'b' in register 'f' is cleared.
BTFSC f,b Syntax: Operands: Operation: Status Affected: Encoding: Description:
Bit Test, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None
01 10bb bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is skipped. If bit 'b' is '0' then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a 2 cycle instruction.
Before Instruction After Instruction
FLAG_REG = 0x47
Words: Cycles: Example
1 1(2)
HERE FALSE TRUE BTFSC GOTO * * * PC = FLAG,1 PROCESS_CODE
Before Instruction
address HERE
After Instruction
if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE
BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None
01 01bb bfff ffff Bit 'b' in register 'f' is set.
f,b
1 1
BSF FLAG_REG, 7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
(c) 1996 Microchip Technology Inc.
DS30559A-page 77
PIC16C64X & PIC16C66X
BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None
01 11bb bfff ffff If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a 2 cycle instruction.
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z
00 0001 1fff ffff The contents of register 'f' are cleared and the Z bit is set.
f
1 1
CLRF FLAG_REG FLAG_REG = = = 0x5A 0x00 1
Words: Cycles: Example
1 1(2)
HERE FALSE TRUE BTFSC GOTO * * * PC = FLAG,1 PROCESS_CODE
Before Instruction After Instruction
FLAG_REG Z
Before Instruction
address HERE
After Instruction
if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None
10 0kkk kkkk kkkk Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two cycle instruction.
CLRW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear W [ label ] CLRW None 00h (W) 1Z Z
00 0001 0000 0011 W register is cleared. Zero bit (Z) is set.
Status Affected: Encoding: Description:
1 1
CLRW
Words: Cycles: Example
1 2
HERE CALL THERE
Before Instruction
W W Z = = = 0x5A 0x00 1
After Instruction
Before Instruction
PC = Address HERE
After Instruction
PC = Address THERE TOS = Address HERE+1
DS30559A-page 78
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD
00 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
DECF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (dest) Z
00 0011 dfff ffff Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Status Affected: Encoding: Description:
Words: Cycles: Example
1 1
DECF CNT, 1 CNT Z = = = = 0x01 0 0x00 1
Words: Cycles: Example
1 1
CLRWDT
Before Instruction
Before Instruction
WDT counter = ? 0x00 0 1 1
After Instruction
CNT Z
After Instruction
WDT counter = WDT prescaler = TO = PD =
COMF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (dest) Z
00 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.
DECFSZ f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (dest); None
00 1011 dfff ffff
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two cycle instruction.
skip if result = 0
Words: Cycles: Example
1 1
COMF REG1,0 REG1 = = = 0x13 0x13 0xEC
Words: Cycles: Example
1 1(2)
DECFSZ GOTO CONTINUE * * * HERE CNT, 1 LOOP
Before Instruction After Instruction
REG1 W
Before Instruction
PC =
address HERE CNT - 1 0, address CONTINUE 0, address HERE+1
After Instruction
CNT if CNT PC if CNT PC = = = =
(c) 1996 Microchip Technology Inc.
DS30559A-page 79
PIC16C64X & PIC16C66X
GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None
10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction.
INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (dest), skip if result = 0 None
00 1111 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two cycle instruction.
Words: Cycles: Example
1 2
GOTO THERE
Words: Cycles:
Address THERE
1 1(2)
HERE INCFSZ GOTO CONTINUE * * * CNT, LOOP 1
After Instruction
PC =
Example
Before Instruction
PC = address HERE CNT + 1 0, address CONTINUE 0, address HERE +1
After Instruction
CNT = if CNT= PC = if CNT PC =
INCF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (dest) Z
00 1010 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z
11 1000 kkkk kkkk The contents of the W register is OR'ed with the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Example
1 1
IORLW W 0x35 = = = 0x9A 0xBF 1
Words: Cycles: Example
1 1
INCF CNT, 1 CNT Z = = = = 0xFF 0 0x00 1
Before Instruction After Instruction
W Z
Before Instruction
After Instruction
CNT Z
DS30559A-page 80
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (dest) Z
00 0100 dfff ffff Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z
00 1000 dfff ffff The contents of register f is moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected.
Words: Cycles: Example
1 1
IORWF RESULT, 0 RESULT = W = 0x13 0x91 0x13 0x93 1
Words: Cycles: Example
1 1
MOVF FSR, 0 W = value in FSR register Z =1
Before Instruction
After Instruction
RESULT = W = Z =
After Instruction
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move Literal to W [ label ] k (W) None
11 00xx kkkk kkkk The eight bit literal 'k' is loaded into W register. The don't cares will assemble as 0's.
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Move W to f [ label ] (W) (f) None
00 0000 1fff ffff Move data from W register to register 'f'.
MOVLW k
MOVWF
f
0 k 255
0 f 127
1 1
MOVWF OPTION OPTION = W = 0xFF 0x4F 0x4F 0x4F
Words: Cycles: Example
1 1
MOVLW W 0x5A = 0x5A
Before Instruction
After Instruction
After Instruction
OPTION = W =
(c) 1996 Microchip Technology Inc.
DS30559A-page 81
PIC16C64X & PIC16C66X
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
NOP
No Operation [ label ] None No operation None
00 0000 0xx0 0000
RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return from Interrupt [ label ] None TOS PC, 1 GIE None
00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two cycle instruction.
NOP
RETFIE
No operation.
Words: Cycles: Example
1 2
RETFIE
After Interrupt
PC = GIE = TOS 1
OPTION Syntax: Operands: Operation: Encoding: Description:
Load Option Register [ label ] None (W) OPTION
00 0000 0110 0010
RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None
11 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
OPTION
Status Affected: None
The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.
Words: Cycles: Example
1 1
To maintain upward compatibility with future PIC16CXX products, do not use this instruction.
Words: Cycles: Example
1 2
CALL TABLE * * * TABLE ADDWF RETLW RETLW * * * RETLW ;W contains table ;offset value ;W now has table value ;W = offset ;Begin table ;
PC k1 k2
kn
; End of table
Before Instruction
W W = = 0x07 value of k8
After Instruction
DS30559A-page 82
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description: Return from Subroutine [ label ] None TOS PC None
00 0000 0000 1000 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.
RRF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. C Register f
RETURN
Words: Cycles: Example
1 2
RETURN
After Interrupt
PC = TOS
Words: Cycles: Example
1 1
RRF REG1 C REG1,0 = = = = = 1110 0110 0 1110 0110 0111 0011 0
Before Instruction
After Instruction
REG1 W C
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C
00 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. C Register f
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD
00 0000 0110 0011 The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Power-Down Mode (SLEEP) for more details.
RLF
f,d
SLEEP
Status Affected: Encoding: Description:
Words: Cycles: Example
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
Words: Cycles: Example:
1 1 SLEEP
Before Instruction
After Instruction
REG1 W C
(c) 1996 Microchip Technology Inc.
DS30559A-page 83
PIC16C64X & PIC16C66X
SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) C, DC, Z 11 110x kkkk kkkk Operation: Status Affected: Encoding: Description: SUBWF Syntax: Operands: Subtract W from f [ label ] 0 f 127 d [0,1] (f) - (W) (dest) C, DC, Z 00 0010 dfff ffff SUBWF f,d
The W register is subtracted (2's complement method) from the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Example 1:
1 1 SUBLW 0x02
W C = = 1 ?
Subtract (2's complement method) W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Words: Cycles: Example 1:
1 1 SUBWF
REG1 W C
Before Instruction
REG1,1
= = = 3 2 ?
Before Instruction
After Instruction
W C = = 1 1; result is positive
Example 2:
Before Instruction
W C = = 2 ?
After Instruction
REG1 W C = = = 1 2 1; result is positive
After Instruction
W C = = 0 1; result is zero
Example 2:
Before Instruction
REG1 W C = = = 2 2 ?
Example 3:
Before Instruction
W C = = 3 ?
After Instruction
REG1 W C = = = 0 2 1; result is zero
After Instruction
W= C = tive 0xFF 0; result is nega-
Example 3:
Before Instruction
REG1 W C = = = 1 2 ?
After Instruction
REG1 W C = = = 0xFF 2 0; result is negative
DS30559A-page 84
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
SWAPF Syntax: Operands: Operation: Status Affected: Encoding: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) None
00
XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z 11 1010 kkkk kkkk
The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register.
1110
dfff
ffff
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.
Words: Cycles: Example:
1 1 XORLW 0xAF
W = 0xB5
Words: Cycles: Example
1 1
SWAPF REG, 0
Before Instruction After Instruction
W = = 0xA5 0x5A = 0x1A
Before Instruction
REG1 = 0xA5
After Instruction
REG1 W
TRIS Syntax: Operands: Operation: Encoding: Description:
Load TRIS Register [ label ] TRIS 5f7 (W) TRIS register f; f
XORWF Syntax: Operands: Operation:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (dest) Z
00 0110 dfff ffff Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
Status Affected: None
00
0000
0110
0fff
Status Affected: Encoding: Description:
The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them.
Words: Cycles: Example
1 1
To maintain upward compatibility with future PIC16CXX products, do not use this instruction.
Words: Cycles: Example
1 1 XORWF
REG 1
Before Instruction
REG W = = 0xAF 0xB5
After Instruction
REG W = = 0x1A 0xB5
(c) 1996 Microchip Technology Inc.
DS30559A-page 85
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 86
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
11.0
11.1
DEVELOPMENT SUPPORT
Development Tools
11.3
ICEPIC: Low-cost PIC16CXX In-Circuit Emulator
The PIC16/17 microcontrollers are supported with a full range of hardware and software development tools: * PICMASTER/PICMASTER CE Real-Time In-Circuit Emulator * ICEPIC Low-Cost PIC16C5X and PIC16CXX In-Circuit Emulator * PRO MATE(R) II Universal Programmer * PICSTART(R) Plus Entry-Level Prototype Programmer * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLAB-SIM Software Simulator * MPLAB-C (C Compiler) * Fuzzy logic development system (fuzzyTECH(R)-MP)
ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC16C5X and PIC16CXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT(R) through PentiumTM based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.
11.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC16C5X, PIC16CXX, PIC17CXX and PIC14000 devices. It can also set configuration and code-protect bits in this mode.
11.2
PICMASTER: High Performance Universal In-Circuit Emulator with MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXX and PIC17CXX families. PICMASTER is supplied with the MPLABTM Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. Interchangeable target probes allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers. The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows(R) 3.x environment were chosen to best make these features available to you, the end user. A CE compliant version of PICMASTER is available for European Union (EU) countries.
11.5
PICSTART Plus Entry Level Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12C5XX, PIC14000, PIC16C5X, PIC16CXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923 and PIC16C924 may be supported with an adapter socket.
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 87
PIC16C64X & PIC16C66X
11.6 PICDEM-1 Low-Cost PIC16/17 Demonstration Board
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. PICDEM3 will be available in the 3rd quarter of 1996.
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-16B programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
11.9
MPLAB Integrated Development Environment Software
The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PIC16/17 tools (automatically updates all project information) * Debug using: - source files - absolute listing file * Transfer data dynamically via DDE (soon to be replaced by OLE) * Run up to four emulators on the same PC The ability to use MPLAB with Microchip's simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.
11.7
PICDEM-2 Low-Cost PIC16CXX Demonstration Board
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-16C, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
11.8
PICDEM-3 Low-Cost PIC16CXX Demonstration Board
The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include
11.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers.
DS30559A-page 88
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
MPASM allows full symbolic debugging from the Microchip Universal Emulator System (PICMASTER). MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PIC16/17. Directives are helpful in making the development of your assemble source code shorter and more maintainable. Both versions include Microchip's fuzzyLABTM demonstration board for hands-on experience with fuzzy logic systems implementation.
11.14
MP-DriveWayTM - Application Code Generator
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually configure all the peripherals in a PIC16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip's MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.
11.15
SEEVAL(R) Evaluation and Programming System
11.11
Software Simulator (MPLAB-SIM)
The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart SerialsTM and secure serials. The Total EnduranceTM Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system.
The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PIC16/17 series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
11.16
TrueGauge(R) Intelligent Battery Management
11.12
C Compiler (MPLAB-C)
The MPLAB-C Code Development System is a complete `C' compiler and integrated development environment for Microchip's PIC16/17 family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display (PICMASTER emulator software versions 1.13 and later).
The TrueGauge development tool supports system development with the MTA11200B TrueGauge Intelligent Battery Management IC. System design verification can be accomplished before hardware prototypes are built. User interface is graphically-oriented and measured data can be saved in a file for exporting to Microsoft Excel.
11.17
KEELOQ(R) Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
11.13
Fuzzy Logic Development System (fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, edition for implementing more complex systems.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 89
Product
MPLABTM C Compiler
TABLE 11-1:
PIC12C508, 509 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006005 SW006006 SW006006 SW006006 SW006006 SW006006 SW006006 SW006006 -- SW006006 SW006006 SW006006 SW006006 -- SW006006 -- --
** MPLABTM Integrated Development Environment SW007002 SW006005 MP-DriveWay Applications Code Generator --
fuzzyTECH(R)-MP Explorer/Edition Fuzzy Logic Dev. Tool --
DS30559A-page 90
DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 --
PIC14000
SW007002
PIC16C52, 54, 54A, 55, 56, 57, 58A PIC16C554, 556, 558
SW007002
SW007002
PIC16C61
SW007002
PIC16C62, 62A, 64, 64A PIC16C620, 621, 622
SW007002
SW007002
SW007002
PIC16C63, 65, 65A, 73, 73A, 74, 74A PIC16C641, 642, 661, 662* PIC16C71
SW007002
SW007002
PIC16C710, 711
SW007002
PIC16C64X & PIC16C66X
DEVELOPMENT TOOLS FROM MICROCHIP
Preliminary
DV005001/ DV005002 DV005001/ DV005002 -- DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 SEEVAL(R) Designers Kit DV243001 N/A N/A DV114001 N/A N/A PG306001
PIC16C72
SW007002
PIC16F83
SW007002
PIC16C84
SW007002
PIC16F84
SW007002
PIC16C923, 924*
SW007002
PIC17C42, SW007002 SW006005 SW006006 42A, 43, 44 *Contact Microchip Technology for availability date **MPLAB Integrated Development Environment includes MPLAB-SIM Simulator and MPASM Assembler
****PRO MATETM PICSTART(R) Lite PICSTART(R) Plus *** PICMASTER(R)/ ICEPIC Low-Cost PICMASTER-CE Ultra Low-Cost Low-Cost II Universal In-Circuit In-Circuit Dev. Kit Universal Microchip Emulator Emulator Dev. Kit Programmer EM167015/ -- DV007003 -- DV003001 EM167101 EM147001/ -- DV007003 -- DV003001 EM147101 EM167015/ EM167201 DV007003 DV162003 DV003001 EM167101 EM167033/ --DV007003 -- DV003001 EM167113 EM167021/ EM167205 DV007003 DV162003 DV003001 N/A EM167025/ EM167203 DV007003 DV162002 DV003001 EM167103 EM167023/ EM167202 DV007003 DV162003 DV003001 EM167109 EM167025/ EM167204 DV007003 DV162002 DV003001 EM167103 EM167035/ --DV007003 DV162002 DV003001 EM167105 EM167027/ EM167205 DV007003 DV162003 DV003001 EM167105 EM167027/ -- DV007003 DV162003 DV003001 EM167105 EM167025/ -- DV007003 DV162002 DV003001 EM167103 EM167029/ -- DV007003 DV162003 DV003001 EM167107 EM167029/ EM167206 DV007003 DV162003 DV003001 EM167107 EM167029/ -- DV007003 DV162003 DV003001 EM167107 EM167031/ -- DV007003 -- DV003001 EM167111 EM177007/ -- DV007003 -- DV003001 EM177107 ***All PICMASTER and PICMASTER-CE ordering part numbers above include PRO MATE II programmer ****PRO MATE socket modules are ordered separately. See development systems ordering guide for specific ordering part numbers Hopping Code Security Programmer Kit N/A Hopping Code Security Eval/Demo Kit N/A N/A DM303001
(c) 1996 Microchip Technology Inc.
Product All 2 wire and 3 wire Serial EEPROM's MTA11200B HCS200, 300, 301 *
TRUEGAUGE(R) Development Kit N/A
PIC16C64X & PIC16C66X
12.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Ambient Temperature under bias ............................................................................................................. -40 to +125C Storage Temperature ............................................................................................................................... -65 to +150C Voltage on any pin with respect to VSS (except VDD and MCLR) .....................................................-0.3V to VDD + 0.3V Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V Voltage on MCLR with respect to VSS (Note 2) .................................................................................................0 to +14V Total power Dissipation (Note 1) ...............................................................................................................................1.0W Maximum Current out of VSS pin ..........................................................................................................................300 mA Maximum Current into VDD pin .............................................................................................................................250 mA Input Clamp Current, IIK (VI<0 or VI> VDD) .......................................................................................................................20 mA Output Clamp Current, IOK (Vo <0 or Vo>VDD) ................................................................................................................20 mA Maximum Output Current sunk by any I/O pin ........................................................................................................25 mA Maximum Output Current sourced by any I/O pin...................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 2) ...................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 2) ..............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 2)..................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 2).............................................................200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: PORTD and PORTE are not implemented on the PIC16C641 and PIC16C642. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 12-1:
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C641-10 PIC16C642-10 PIC16C661-10 PIC16C662-10 VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4.5V to 5.5V 2.7 mA typ. @ 5.5V 1.5 A typ. @ 4.0V 4.0 MHz max. 4.5V to 5.5V 2.7 mA typ. @ 5.5V 1.5 A typ. @ 4.0V 4.0 MHz max. 4.5V to 5.5V 30 mA max. @ 5.5V 1.5 A typ. @ 4.5V 10 MHz max. VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: PIC16C641-20 PIC16C642-20 PIC16C661-20 PIC16C662-20 4.5V to 5.5V 2.7 mA typ. @ 5.5V 1.5 A typ. @ 4.0V 4.0 MHz max. 4.5V to 5.5V 2.7 mA typ. @ 5.5V 1.5 A typ. @ 4.0V 4.0 MHz max. VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: PIC16LC641-04 PIC16LC642-04 PIC16LC661-04 PIC16LC662-04 3.0V to 6.0V 2.0 mA typ. @ 3.0V 0.9 A typ. @ 3.0V 4.0 MHz max. 3.0V to 6.0V 2.0 mA typ. @ 3.0V 0.9 A typ. @ 3.0V 4.0 MHz max. VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq:
OSC
PIC16C641-04 PIC16C642-04 PIC16C661-04 PIC16C662-04 VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4.0V to 6.0V 5 mA max. @ 5.5V 21 A max. @ 4.0V 4.0 MHz max. 4.0V to 6.0V 5 mA max. @ 5.5V 21 A max. @ 4.0V 4.0 MHz max. 4.5V to 5.5V 13.5 mA typ. @ 5.5V 1.5 A typ. @ 4.5V 4.0 MHz max.
JW Devices
RC
4.0V to 6.0V 5 mA max. @ 5.5V 21 A max. @ 4.0V 4.0 MHz Max. 4.0V to 6.0V 5 mA max. @ 5.5V 21 A max. @ 4.0V 4.0 MHz max. 4.5V to 5.5V 30 mA max. @ 5.5V 1.5 A typ. @ 4.5V 10 MHz max.
XT
HS
Do not use in HS mode 4.5V to 5.5V 30 mA max. @ 5.5V 1.5 A typ. @ 4.5V 20 MHz max. VDD: 3.0V to 6.0V IDD: 48 A max. @ 32 kHz, 3.0V IPD: 5.0 A max. @ 3.0V Freq: 200 kHz max.
LP
VDD: 4.0V to 6.0V IDD: 52.5 A typ. @ 32 kHz, 4.0V IPD: 0.9 A typ. @ 4.0V Freq: 200 kHz max.
Do not use in LP mode
Do not use in LP mode
VDD: 3.0V to 6.0V IDD: 48 A max. @ 32 kHz, 3.0V IPD: 5.0 A max. @ 3.0V Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 91
PIC16C64X & PIC16C66X
12.1 DC Characteristics: PIC16C641/642/661/662-04 (Commercial, Industrial, Automotive) PIC16C641/642/661/662-10 (Commercial, Industrial, Automotive) PIC16C641/642/661/662-20 (Commercial, Industrial, Automotive)
Sym Param No. D001 VDD D001A D002* VDR D003 VPOR
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial, 0C TA +70C commercial, and -40C TA +125C automotive Characteristic Min Typ Max Units Supply Voltage RAM Data Retention Voltage(1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Supply Current(2) 4.0 4.5 1.5 - - - - VSS 6.0 5.5 - - V V V V
Conditions
XT, RC and LP osc configuration HS osc configuration Device in SLEEP mode See section on Power-on Reset for details
D004* D005 D010
SVDD VBOR IDD
0.05 3.7 3.7 -
- 4.0 4.0 2.7
- 4.3 4.4 5
D010A
-
35
70
D013
-
13.5
30
V/ms See section on Power-on Reset for details V BODEN configuration bit is clear V Automotive mA XT and RC osc configuration FOSC = 4 MHz, VDD = 5.5V, WDT disabled (4) A LP osc configuration, PIC16C64X & PIC16C66X-04 only FOSC = 32 kHz, VDD = 4.0V, WDT disabled mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V, WDT disabled A A BODEN bit is clear, VDD = 5.0V VDD = 4.0V
D015 D016 D017 D021
IBOR ICOMP IVREF IWDT
- - 300 A VDD = 4.0V - 6.0 20 A VDD = 4.0V - - 25 A Automotive (3) D021 IPD - 1.5 21 A VDD = 4.0V, WDT disabled Power-down Current - 2.5 24 A Automotive * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-statedTM, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in k. 5: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
Module Differential Current (5) Brown-out Reset Current Comparator Current for each Comparator VREF Current WDT Current
- -
350 -
425 100
DS30559A-page 92
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
12.2 DC Characteristics: PIC16LC641/642/661/662-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C commercial Characteristic Min Typ Max Units Supply Voltage 3.0 RAM Data Retention 1.5 Voltage (1) VDD start voltage to - ensure internal Power-on Reset signal VDD rise rate to ensure internal 0.05 Power-on Reset signal Brown-out Reset Voltage 3.7 (2) - Supply Current - - VSS 6.0 - - V V V
Param Sym No. D001 VDD D002* VDR D003 VPOR
Conditions
XT, RC, and LP osc configuration Device in SLEEP mode See section on Power-on Reset for details
D004* D005 D010
SVDD VBOR IDD
- 4.0 2.0
- 4.3 3.8
V/ms See section on Power-on Reset for details V BODEN configuration bit is clear mA XT and RC osc configuration FOSC = 4.0 MHz, VDD = 3.0V, WDT disabled (4) A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled BODEN bit is clear, VDD = 5.0V VDD = 3.0V VDD = 3.0V VDD = 3.0V VDD = 3.0V, WDT disabled
D010A
-
22.5
48
D015 D016 D017 D021 D021
IBOR ICOMP IVREF IWDT IPD
Module Differential Current (5) Brown-out Reset Current Comparator Current for each Comparator VREF Current WDT Current
- - - - -
350 - - 6.0 0.9
425 100 300 20 5
A A A A A
Power-down Current (3) * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in k. 5: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 93
PIC16C64X & PIC16C66X
12.3 DC Characteristics: PIC16C641/661 (Commercial, Industrial, Automotive) PIC16C642/662 (Commercial, Industrial, Automotive) PIC16LC641/661 (Commercial, Industrial) PIC16LC642/662 (Commercial, Industrial)
Param No.
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial, 0C TA +70C commercial, and -40C TA +125C automotive Operating voltage VDD range as described in DC spec Section 12.1 and 12.2 Sym Characteristic Min Typ Max Unit VIL Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger input MCLR, RA4/T0CKI,OSC1 (in RC mode) OSC1 (XT and HS modes) OSC1 (LP modes) Input High Voltage I/O ports with TTL buffer with Schmitt Trigger input MCLR RA4/T0CKI OSC1 (XT, HS, LP modes) OSC1 (RC mode) PORTB weak pull-up current Input Leakage I/O ports (Except PORTA) Current(2,3) 1.0 0.5 1.0 5.0 A A A A
Conditions
D030 D031 D032 D033 VIH D040 D041 D042 D043 D043A D070 IPURB IIL
VSS VSS VSS Vss Vss Vss
-
0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD 0.6VDD-1.0
V V V V V V
For entire VDD range 4.5V VDD 5.5V
(1)
2.0 0.25VDD to 0.8V 0.8VDD 0.7VDD 0.9VDD 50 200
VDD VDD VDD VDD 400
V V V V V A
(1)
VDD = 5.0V, VPIN = VSS
D060 D061 D063 VOL D080
PORTA RA4/T0CKI OSC1, MCLR Output Low Voltage I/O ports
-
VSS VPIN VDD, pin at hi-impedance Vss VPIN VDD, pin at hi-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V, -40 to +85C IOL = 7.0 MA, VDD = 4.5V, +125C IOL = 1.6 mA, VDD = 4.5V, -40 to +85C IOL = 1.2 mA, VDD = 4.5V, +125C
-
-
0.6 0.6 0.6
V V V
D083
OSC2/CLKOUT
(RC only) 0.6 V * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C64X & PIC16C66X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin.
DS30559A-page 94
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial, 0C TA +70C commercial, and -40C TA +125C automotive Operating voltage VDD range as described in DC spec Section 12.1 and 12.2 Sym Characteristic Min Typ Max Unit VOH D090 Output High Voltage (3) I/O ports (Except RA4)
Param No.
Conditions
VDD-0.7 VDD-0.7
-
-
V V V V
D092
OSC2/CLKOUT
VDD-0.7 VDD-0.7
D100
(RC only) Capacitive Loading Specs on Output Pins COSC2 OSC2 pin
IOH = -3.0 mA, VDD = 4.5V, -40 to +85C IOH = -2.5 mA, VDD = 4.5V, +125C IOH = -1.3 mA, VDD=4.5V, -40 to +85C IOH = -1.0 mA, VDD = 4.5V, +125C
-
-
15
pF
In XT, HS and LP modes when external clock used to drive OSC1.
D101 CIO All I/O pins/OSC2 (in RC mode) 50 pF * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C64X & PIC16C66X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 95
PIC16C64X & PIC16C66X
TABLE 12-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 6.0V, -40C < TA < +125C, unless otherwise stated. Current consumption is specified in Table 12-1. Characteristics Input offset voltage Input common mode voltage* CMRR* Response Time(1)* Comparator Mode Change to Output Valid* Sym Min 0 35 Typ 5.0 150 Max 10 VDD - 1.5 400 600 10 Units mV V db ns ns s PIC16C64X/66X PIC16LC64X/66X Comments
* These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD.
TABLE 12-3:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 6.0V, -40C < TA < +125C, unless otherwise stated. Current consumption is specified in Table 12-1. Characteristics Resolution Absolute Accuracy Unit Resistor Value (R)* Settling Time
(1)*
Sym
Min VDD/24 -
Typ 2k -
Max VDD/32 1/4 1/2 10
Units LSb LSb LSb s
Comments Low Range (VRR = 1) High Range (VRR = 0) Figure 8-2
* These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
DS30559A-page 96
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
12.4 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase subscripts (pp) and their meanings: pp ck CLKOUT io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
osc OSC1 t0 T0CKI
P R V Z
Period Rise Valid Hi-Impedance
FIGURE 12-1: LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS RL = CL = 464 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2 for OSC2 output
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 97
PIC16C64X & PIC16C66X
12.5 Timing Diagrams and Specifications FIGURE 12-2: EXTERNAL CLOCK TIMING
Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
TABLE 12-4:
Param No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency(1) Min DC Typ -- Max 4 Units MHz Conditions XT and RC osc mode, VDD = 5.0V HS osc mode LP osc mode RC osc mode, VDD = 5.0V XT osc mode HS osc mode LP osc mode XT and RC osc mode HS osc mode LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode TCY = FOSC/4 XT osc mode LP osc mode HS osc mode XT osc mode LP osc mode HS osc mode
Sym Fosc
DC -- 20 MHz DC -- 200 kHz Oscillator Frequency (1) DC -- 4 MHz 0.1 -- 4 MHz 4 -- 20 MHz 5 - 200 kHz 1 Tosc External CLKIN Period(1) 250 -- -- ns 50 -- -- ns 5 -- -- s Oscillator Period(1) 250 -- -- ns 250 -- 10,000 ns 50 -- 250 ns 5 -- -- s 2 TCY Instruction Cycle Time(1) 200 -- DC ns 3* TosL, External Clock in (OSC1) 100 -- -- ns TosH High or Low Time 2.5 -- -- s 15 -- -- ns 4* TosR, External Clock in (OSC1) -- -- 25 ns TosF Rise or Fall Time -- -- 50 ns -- -- 15 ns * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30559A-page 98
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 12-3: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 15 new value 19 11 Q1 Q2 Q3
22 23
18 12 16
20, 21 Note: See Figure 12-1 for load conditions.
TABLE 12-5:
Parameter Sym No. 10* 11* 12* 13* 14* 15* 16* 17* 18*
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time PIC16C64X/66X PIC16LC64X/66X Min -- -- -- -- -- TOSC + 200 0 -- 100 200 0 -- -- -- -- TCY TCY Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 0.5TCY + 20 -- -- 150 -- -- -- 40 80 40 80 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
TosH2ckL TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI
TosH2ckH OSC1 to CLKOUT
19* 20* 21* 22* 23* *
TioV2osH TioR TioF Tinp Trbp
Port input valid to OSC1 (I/O in setup time) PIC16C64X/66X PIC16LC64X/66X PIC16C64X/66X PIC16LC64X/66X
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 99
PIC16C64X & PIC16C66X
FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Timeout OSC Timeout Internal RESET Parity Error Reset 36 Watchdog Timer RESET 32 30
34 31 34
I/O Pins
FIGURE 12-5: BROWN-OUT RESET TIMING
VDD BVDD 35
TABLE 12-6:
Parameter No. 30 31* 32 33* 34 35 36 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ TBOR TPER Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset pulse width Parity Error Reset Min 2 7 -- 28 -- 100 -- Typ -- 18 1024TOSC 72 -- -- TBD Max -- 33 -- 132 2.1 -- -- Units s ms -- ms s s s VDD BVDD (D005) Conditions VDD = 5V, -40C to +125C VDD = 5V, -40C to +125C TOSC = OSC1 period VDD = 5V, -40C to +125C
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30559A-page 100
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 12-6: TIMER0 CLOCK TIMING
RA4/T0CKI
40 42
41
TMR0
TABLE 12-7:
Param Sym No. 40* 41* 42*
TIMER0 CLOCK REQUIREMENTS
Characteristic No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 40 N Typ Max Units -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns Conditions
Tt0H T0CKI High Pulse Width Tt0L T0CKI Low Pulse Width Tt0P T0CKI Period
N = prescale value (1, 2, 4, ..., 256)
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 101
PIC16C64X & PIC16C66X
FIGURE 12-7: PARALLEL SLAVE PORT TIMING (PIC16C661 AND PIC16C662)
RE2/CS
RE0/RD
RE1/WR
65 RD7:RD0 62 63 Note: Refer to Figure 12-1 for load conditions
64
TABLE 12-8:
Parameter No. 62 63*
PARALLEL SLAVE PORT REQUIREMENTS (PIC16C661 AND PIC16C662)
Sym Characteristic Min Typ Max Units 20 20 35 -- 10 -- -- -- -- -- -- -- -- 80 30 ns ns ns ns ns Conditions
TdtV2wrH Data in valid before WR or CS (setup time) TwrH2dtI WR or CS to data-in invalid (hold time) PIC16C66X PIC16LC66X
64 65
TrdL2dtV TrdH2dtI
RD and CS to data-out valid RD or CS to data-out invalid
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30559A-page 102
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
13.0 DEVICE CHARACTERIZATION INFORMATION
NOT AVAILABLE AT THIS TIME.
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 103
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 104
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
14.0 PACKAGING INFORMATION
Package Type: 28-Lead Skinny Plastic Dual In-Line (SP) - 300 mil
E1 Pin No. 1 Indicator Area
E eA eB
C
B2 Base Plane Seating Plane Detail A D1 B3 S D
B1
L e1 A1A2A B Detail A
Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol A A1 A2 B B1 B2 B3 C D D1 E E1 e1 eA eB L S Min 3.632 0.381 3.175 0.406 1.016 0.762 0.203 0.203 34.163 33.020 7.874 7.112 2.540 7.874 8.128 3.175 0.584 Max 4.572 -- 3.556 0.559 1.651 1.016 0.508 0.331 35.179 33.020 8.382 7.493 2.540 7.874 9.906 3.683 1.220 Notes Min 0.143 0.015 0.125 0.016 0.040 0.030 0.008 0.008 1.385 1.300 0.310 0.280 0.100 0.310 0.320 0.125 0.023 Inches Max 0.180 -- 0.140 0.022 0.065 0.040 0.020 0.013 1.395 1.300 0.330 0.295 0.100 0.310 0.390 0.145 0.048 Notes
Typical 4 places 4 places Typical BSC
Typical 4 places 4 places Typical BSC
Typical BSC
Typical BSC
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 105
PIC16C64X & PIC16C66X
Package Type: 28-Lead Plastic Small Outline (SO) - Wide, 300 mil Body
e B
h x 45 Pin No. 1 Indicator Area Chamfer h x 45
E
H L
C
D
Seating Plane
CP
Base Plane
A1
A
Package Group: Plastic SOIC (SO) Millimeters Symbol A A1 B C D E e H h L CP Min 0 2.362 0.101 0.355 0.241 17.703 7.416 1.270 10.007 0.381 0.406 -- Max 8 2.642 0.300 0.483 0.318 18.085 7.595 1.270 10.643 0.762 1.143 0.102 Notes Min 0 0.093 0.004 0.014 0.009 0.697 0.292 0.050 0.394 0.015 0.016 -- Inches Max 8 0.104 0.012 0.019 0.013 0.712 0.299 0.050 0.419 0.030 0.045 0.004 Notes
BSC
BSC
DS30559A-page 106
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Package Type: 28-Lead Ceramic Side Brazed Dual In-Line with Window (JW) (300 mil)
E1 E
eA eB
C
Pin No. 1 Indicator Area D S1 Base Plane Seating Plane B1 B D1 e1 S
L
A3 A1 A
A2
Package Group: Ceramic Side Brazed Dual In-Line (CER) Millimeters Symbol Min A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L S S1 0 3.937 1.016 2.921 1.930 0.406 1.219 0.228 35.204 32.893 7.620 7.366 2.413 7.366 7.594 3.302 1.143 0.533 Max 10 5.030 1.524 3.506 2.388 0.508 1.321 0.305 35.916 33.147 8.128 7.620 2.667 7.874 8.179 4.064 1.397 0.737 Notes Min 0 0.155 0.040 0.115 0.076 0.016 0.048 0.009 1.386 1.295 0.300 0.290 0.095 0.290 0.299 0.130 0.045 0.021 Max 10 0.198 0.060 0.138 0.094 0.020 0.052 0.012 1.414 1.305 0.320 0.300 0.105 0.310 0.322 0.160 0.055 0.029 Notes Inches
Typical Typical BSC
Typical BSC
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 107
PIC16C64X & PIC16C66X
Package Type: 40-Lead Ceramic Dual In-Line with Window (JW) - (600 mil)
E1 Pin No. 1 Indicator Area D Base Plane Seating Plane B1 B e1 D1 S S1
E
eA eB
C
L A1A3 A A2
Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Symbol A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L S S1 Min 0 4.318 0.381 3.810 3.810 0.355 1.270 0.203 51.435 48.260 15.240 12.954 2.540 14.986 15.240 3.175 1.016 0.381 Max 10 5.715 1.778 4.699 4.445 0.585 1.651 0.381 52.705 48.260 15.875 15.240 2.540 16.002 18.034 3.810 2.286 1.778 Notes Min 0 0.170 0.015 0.150 0.150 0.014 0.050 0.008 2.025 1.900 0.600 0.510 0.100 0.590 0.600 0.125 0.040 0.015 Inches Max 10 0.225 0.070 0.185 0.175 0.023 0.065 0.015 2.075 1.900 0.625 0.600 0.100 0.630 0.710 0.150 0.090 0.070 Notes
Typical Typical BSC
Typical Typical BSC
BSC Typical
BSC Typical
DS30559A-page 108
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Package Type: 40-Lead Plastic Dual In-Line (P) - 600 mil
E1 Pin No. 1 Indicator Area D Base Plane Seating Plane B1 B S S1
E eA eB
C
L e1 D1 A1A2 A
Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol A A1 A2 B B1 C D D1 E E1 e1 eA eB L S S1 Min -- 0.381 3.175 0.355 1.270 0.203 51.181 48.260 15.240 13.462 2.489 15.240 15.748 2.921 1.270 0.508 Max 5.080 -- 4.064 0.559 1.778 0.381 52.197 48.260 15.875 13.970 2.591 15.240 17.272 3.683 -- -- Notes Min -- 0.015 0.125 0.014 0.050 0.008 2.015 1.900 0.600 0.530 0.098 0.600 0.620 0.115 0.050 0.020 Inches Max 0.200 -- 0.160 0.022 0.070 0.015 2.055 1.900 0.625 0.550 0.102 0.600 0.680 0.145 -- -- Notes
Typical Typical BSC
Typical Typical BSC
Typical BSC
Typical BSC
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 109
PIC16C64X & PIC16C66X
Package Type: 44-Lead Plastic Leaded Chip Carrier (L) - Square
D/2 D 0.177 .007 S B D-E S D1 -A-D3 0.38 .015 0.38 .015 1.27 .050 2 Sides A D3/E3 D2 3 -GE1 -BE F-G S E2 F-G S 4 E/2 4 0.812/0.661 N Pics .032/.026 -HA1 D -C0.177 .007 S B A S 2 Sides 9
0.101 Seating .004 Plane
3 -F-
8
3
-E-
0.177 .007 S A F-G S 10 0.254 .010 Max 0.508 .020 6 -C1.651 .065 R 1.14/0.64 .045/.025 1.651 .065 R 1.14/0.64 .045/.025 0.64 Min .025 5 0.533/0.331 .021/.013 0.177 , D-E S .007 M A F-G S 0.812/0.661 3 .032/.026
0.254 .010 Max 2 -H6
11
11 0.508 .020 -H2
1.524 .060 Min
Package Group: Plastic Leaded Chip Carrier (PLCC) Millimeters Symbol A A1 D D1 D2 D3 E E1 E2 E3 CP LT Min 4.191 2.413 17.399 16.510 15.494 12.700 17.399 16.510 15.494 12.700 -- 0.203 Max 4.572 2.921 17.653 16.663 16.002 12.700 17.653 16.663 16.002 12.700 0.102 0.381 Notes Min 0.165 0.095 0.685 0.650 0.610 0.500 0.685 0.650 0.610 0.500 -- 0.008 Inches Max 0.180 0.115 0.695 0.656 0.630 0.500 0.695 0.656 0.630 0.500 0.004 0.015 Notes
BSC
BSC
BSC
BSC
DS30559A-page 110
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Package Type: 44-Lead Thin Plastic Quad Flatpack (PT/TQ) - 10x10x1 mm Body 1.0/0.10 mm Lead Form
D1 D D/2
PinNo. 1 Indicator Area
E1 e E/2
E
8 Places 11/13
A
0 min.
Detail B
A2 Datum Plane 0.25 0.08 R min. 0.20 min. 1.00 ref. L
b with Lead Finish 0.09/0.20 b1 Base Metal 0.09/0.16
A1
0-7 Gauge Plane
DETAIL B
Package Group: Plastic TQFP Millimeters Symbol A A1 A2 b b1 D D1 E E1 e L Min 0 -- 0.050 0.950 0.300 0.300 12.0 10.0 12.0 10.0 0.8 0.450 Max 7 1.200 0.150 1.050 0.450 0.400 12.0 10.0 12.0 10.0 0.8 0.750 Notes Min 0 -- 0.002 0.037 0.012 0.012 0.472 0.394 0.472 0.394 0.031 0.018 Inches Max 7 0.047 0.006 0.041 0.018 0.016 0.0472 0.394 0.472 0.394 0.031 0.030 Notes
BSC BSC BSC BSC BSC
BSC BSC BSC BSC BSC
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 111
PIC16C64X & PIC16C66X
14.1 Package Marking Information Example PIC16C642-10/SP AABBCDE 28-Lead PDIP (Skinny DIP) MMMMMMMMMMMM XXXXXXXXXXXXXXX AABBCDE
28-Lead SOIC MMMMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXXXX AABBCDE
Example PIC16C642-10/SO 945/CAA
28-Lead Side Brazed Skinny Windowed XXXXXXXXXXX XXXXXXXXXXX AABBCDE
Example PIC16C642/JW 9517CAT
Legend: MM...MMicrochip part number information XX...X Customer specific information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week `01') C Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A. D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note:In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
DS30559A-page 112
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
14.2 Package Marking Information 40-Lead PDIP MMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXX AABBCDE Example PIC16C662-04/P 9512CAA
40-Lead CERDIP Windowed
Example
MMMMMMMMM XXXXXXXXXXX XXXXXXXXXXX AABBCDE
PIC16C662/JW AABBCDE
44-Lead PLCC
Example
MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE
PIC16C662 -20/L AABBCDE
44-Lead TQFP MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE
Example PIC16C662 -20/TQ AABBCDE
Legend: MM...MMicrochip part number information XX...X Customer specific information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week `01') C Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A. D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note:In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 113
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 114
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
APPENDIX A: ENHANCEMENTS
The following are the list of enhancements over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14 bits. This allows larger page sizes both in program memory (4K now as opposed to 512 before) and register file (up to 176 bytes now versus 32 bytes before). A PC high latch register (PCLATH) is added to handle program memory paging. PA2, PA1, PA0 bits are removed from STATUS register. Data memory paging is slightly redefined. STATUS register is modified. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compatibility with PIC16C5X. OPTION and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. Reset vector is changed to 0000h. Reset of all registers is revisited. Six different reset (and wake-up) types are recognized. Registers are reset differently. Wake up from SLEEP through interrupt is added. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These timers can be invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt on change feature. Timer0 clock input, T0CKI pin is also a port pin (RA4/T0CKI) and has a TRIS bit. FSR is made a full 8-bit register. "In-circuit programming" is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, VPP, RB6 (clock) and RB7 (data in/out). PCON status register is added with a Power-on Reset status bit (POR), a Brown-out Reset status bit (BOR), a Parity Error Reset (PER), and a Memory Parity Enable (MPEEN) bit. Code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. PORTA inputs are now Schmitt Trigger inputs. Brown-out Reset circuitry has been added.
APPENDIX B: COMPATIBILITY
To convert code written for PIC16C5X to PIC16CXX, the user should take the following steps: 1. 2. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change reset vector to 0000h.
2.
3. 4. 5.
3. 4.
5. 6. 7. 8. 9.
10. 11.
12. 13. 14. 15.
16.
17.
18. 19.
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 115
PIC16C64X & PIC16C66X
APPENDIX C: WHAT'S NEW
New Data Sheet
APPENDIX D: WHAT'S CHANGED
New Data Sheet
DS30559A-page 116
Preliminary
(c) 1996 Microchip Technology Inc.
E.1 PIC14000 Devices
(c) 1996 Microchip Technology Inc. Clock
Hz )
Memory
Peripherals
Features
io at
n
(M
or
y
)
(x
14
wo
r
) ds
y nc
o
r pe fO
M
em
s te by
I SP
/I
2
C
,U
R SA
T)
am
m
in
g
APPENDIX E: PIC16/17 MICROCONTROLLERS
) r lts gr te ls ro ip Vo s er nne ( e v s) lP am ch ( ( na ( e e r rc nle ria qu ry s) ng og Co Ch ou u e e o a rt( S lO Pr D) Fr R od tS em pt ins na es Po A/ es M ui um M ge rM ru e h-r O rc tio tur al r i e im ri R ta lta di a op ig te /O P m -C ax Se In Sl (h EP I Vo Da Ti Ad Fe M In
Pa
a ck
ge
s
This document was created with FrameMaker 4 0 4
4K 192 TMR0 I2C/ ADTMR SMBus 14 11 22 2.7-6.0 Internal Oscillator, Bandgap Reference, Temperature Sensor, Calibration Factors, Yes Low Voltage Detector, SLEEP, HIBERNATE, Comparators with Programmable References (2)
PIC14000
20
28-pin DIP, SOIC, SSOP (.300 mil)
PIC16C64X & PIC16C66X
DS30559A-page 117
E.2
s)
yte
)
cy of O pe ra tio n P (M ro g Hz (x ram ) 12 M wo em rd or s) y
y( b
lts
en
or
)
qu
(s
(V o
em
le
e
M
ng
In
str u
cti
on
s
Fr e
od u
at a
Ra
of
um
M
D
ns
e
im
OM
M
er
Pi
ag
m
be r
ax
M
EP R
M
RO
RA
Ti m
I/O
PIC16C52 20 20 20 20 20 20 20 20 20 -- 2K 73 TMR0 2K -- 73 TMR0 -- 2K 72 TMR0 20 12 12 2K -- 72 TMR0 20 1K -- 25 TMR0 12 512 -- 24 TMR0 20 2.5-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.0-6.25 2.5-6.25 -- 512 25 TMR0 12 2.0-6.25 512 -- 25 TMR0 12 2.0-6.25 33 33 33 33 33 33 33 33 512 -- 25 TMR0 12 2.5-6.25 33
4
384
--
25
TMR0
12
2.5-6.25
Vo lt
33
Nu
18-pin DIP, SOIC 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 28-pin DIP, SOIC, SSOP 18-pin DIP, SOIC; 20-pin SSOP 28-pin DIP, SOIC, SSOP 28-pin DIP, SOIC, SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP
PIC16C54
PIC16C54A
PIC16C64X & PIC16C66X
PIC16CR54A
PIC16C55
PIC16C56
PIC16C57
PIC16CR57B
PIC16C58A
PIC16CR58A
(c) 1996 Microchip Technology Inc.
All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
P
ac k
ag
es
DS30559A-page 118
PIC16C5X Family of Devices
Clock
Memory
Peripherals
Features
E.3
Clock
Memory
Peripherals
Features
tio
n
(M
er a
p
ta
ge
fO
Hz Pr og ) r (x1 am 4M wo em rd ory s)
cy o
yte
)
ce
(V
olt
en
(s
en
e
)
e
y( b
qu
(s
fe r
rc
or
du le
or
e
ng
Fr e
o
So u
Ra
tR e ou nro w
se
t
M
em
ra t
lR
M
pt
ns
e
um
O
M
pa
rn a
er
ru
im
ta
te
Pi
ag
ax
EP R
m
nt e
In
Da
I/O
Ti
M
Co m
I
Vo lt
B
P
ac k
ag
es
(c) 1996 Microchip Technology Inc.
s)
Vo l
s)
PIC16CXXX Family of Devices
PIC16C554 20 20 20 20 20 20 20 20 2K 128 TMR0 2 Yes 5 4K 176 TMR0 2 Yes 4 22 33 2K 128 TMR0 2 Yes 4 22 2K 128 TMR0 2 Yes 4 13 2.5-6.0 3.0-6.0 3.0-6.0 3.0-6.0 1K 80 TMR0 2 Yes 4 13 2.5-6.0 512 80 TMR0 2 Yes 4 13 2.5-6.0 Yes Yes Yes Yes Yes Yes 2K 128 TMR0 -- -- 3 13 2.5-6.0 -- 1K 80 TMR0 -- -- 3 13 2.5-6.0 --
20
512
80
TMR0
--
--
3
13
2.5-6.0
--
18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 28-pin PDIP, SOIC Windowed CDIP 28-pin PDIP, SOIC Windowed CDIP 40-pin PDIP, Windowed CDIP; 44-pin PLCC, MQFP
PIC16C556
PIC16C558
PIC16C620
PIC16C621
PIC16C622
PIC16C641
PIC16C642
PIC16C661
PIC16C662
20
4K
176
TMR0
2
Yes
5
33
3.0-6.0
Yes
40-pin PDIP, Windowed CDIP; 44-pin PLCC, MQFP
PIC16C64X & PIC16C66X
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C6XXX Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30559A-page 119
E.4
Clock
(M H z)
Memory
s)
Peripherals
Features
DS30559A-page 120
y e( or ) ul g RT em s) od in ti M rd M m SA ra m wo e U m M p , ) ra ra O ) 2C W lts og 14 of og /I /P t es y Vo Pr (x yt t s Pr re or PI ) c ( l s P (b e se ce (S en pa ia e( ur ry m qu ve ng s) er Re ul o e a t( la t So Co Fr R tS od or es em ou lS e/ ui pt ins M M um lP ge nag rM ur lle rc O ru e r P w M im R pt ta lta ck ra ria Ci o m te ax Se Da In In Br Pa Ca EP RO Ti Pa Vo I/O M
on
PIC16C6X Family of Devices
PIC16C62 20 20 20 20 20 20 20 20 20 20 -- 4K 192 TMR0, TMR1, TMR2 4K -- 192 TMR0, TMR1, TMR2 4K -- 192 TMR0, TMR1, TMR2 -- 2K 128 TMR0, TMR1, TMR2 1 SPI/I2C Yes 2K -- 128 TMR0, TMR1, TMR2 1 SPI/I2C Yes 8 8 11 11 2 SPI/I2C, Yes USART 11 2K -- 128 TMR0, TMR1, TMR2 1 SPI/I2C Yes 8 33 33 33 33 33 33 -- 4K 192 TMR0, TMR1, TMR2 2 SPI/I2C, USART -- 10 22 2.5-6.0 3.0-6.0 2.5-6.0 2.5-6.0 3.0-6.0 2.5-6.0 2.5-6.0 4K -- 192 TMR0, TMR1, TMR2 2 SPI/I2C, USART -- 10 22 2.5-6.0 Yes Yes Yes Yes Yes Yes Yes Yes -- 2K 128 TMR0, TMR1, TMR2 1 SPI/I2C -- 7 22 2.5-6.0 Yes 2K -- 128 TMR0, TMR1, TMR2 1 SPI/I2C -- 7 22 2.5-6.0 Yes
20
2K
--
128 TMR0, TMR1, TMR2
1 SPI/I2C -- 7 22 3.0-6.0 Yes --
28-pin SDIP, SOIC, SSOP
PIC16C62A(1)
Yes 28-pin SDIP, SOIC, SSOP Yes 28-pin SDIP, SOIC, SSOP Yes 28-pin SDIP, SOIC Yes 28-pin SDIP, SOIC -- 40-pin DIP; 44-pin PLCC, MQFP Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP -- 40-pin DIP; 44-pin PLCC, MQFP Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP
PIC16CR62(1)
PIC16C63
PIC16C64X & PIC16C66X
PIC16CR63(1)
PIC16C64
PIC16C64A(1)
PIC16CR64(1)
PIC16C65
2 SPI/I2C, Yes USART 2 SPI/I2C, Yes USART
PIC16C65A(1)
PIC16CR65(1)
(c) 1996 Microchip Technology Inc.
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability. All PIC16C6X family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local sales office for availability of these devices.
E.5
Clock
n (M ) Hz
Memory
r ) ds
Peripherals
od ul e( s)
Features
ne ls
(c) 1996 Microchip Technology Inc.
e Fr qu en cy of O r pe io at im um
M
o Pr
gr
am
M
em
o
ry
(
4 x1
wo
RT
b 8it) C n ha
)
PIC16C7X Family of Devices
ax M
RO EP
a
M
em
or
y
(b
e yt
s)
t Da
T
C
im
I
er
t ap
M
ur
o
e/
l du
m Co
e(
s)
pa
/ re
PW
M
M
A US
ve
Co n r ve te
r Se
r Pa
D A/
ia
e nt
l
al
Po
le
rru
s rt(
l a Sl
S pt
)(
ou
I SP
P
rc
r(
/I
t or
es
2
C,
o (V
lts
)
m
g in
I/O
2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 Yes Yes Yes Yes
Pi
ns
am gr ro t lP se ia ge er Re an R es ut tS ui -o ag ge irc ta ck wn l o -C Pa Vo In Br
Yes 18-pin DIP, SOIC; 20-pin SSOP -- 18-pin DIP, SOIC Yes 18-pin DIP, SOIC; 20-pin SSOP Yes 28-pin SDIP, SOIC, SSOP
PIC16C710 20 20 20 20 20 20 20 4K 4K 192 TMR0, 2 SPI/I2C, Yes TMR1, TMR2 USART 192 TMR0, 2 SPI/I2C, Yes TMR1, TMR2 USART 4K 192 TMR0, 2 SPI/I2C, TMR1, TMR2 USART -- 5 8 8 4K 192 TMR0, 2 SPI/I2C, TMR1, TMR2 USART -- 5 11 11 12 12 2K 128 TMR0, 1 SPI/I2C TMR1, TMR2 -- 5 8 22 22 22 33 33 1K 68 TMR0 -- -- -- 4 4 13 1K 36 TMR0 -- -- -- 4 4 13
20
512
36
TMR0
--
--
--
4
4
13
PIC16C71 PIC16C711
PIC16C72
PIC16C73
2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
Yes Yes Yes Yes
--
28-pin SDIP, SOIC Yes 28-pin SDIP, SOIC -- 40-pin DIP; 44-pin PLCC, MQFP Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP
PIC16C73A
PIC16C74
PIC16C74A
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C7X Family devices use serial programming with clock pin RB6 and data pin RB7.
PIC16C64X & PIC16C66X
DS30559A-page 121
E.6
h
as
Fl
DS30559A-page 122 Clock
n tio (M ) Hz
Memory
em
e yt s)
Peripherals
Features
PIC16C8X Family of Devices
or
y
F
q re
ue
n
cy
of
O
pe
ra
Pr
or y (b
M RO M
r og
em
am
M
M
a
xim
um
EE
O PR
Da
ta
M
Da
T
TMR0 TMR0 TMR0 TMR0 TMR0 4 4 4 4 4
ta
im
EE
er M
P
o
RO
M
l du
(
e(
t by
s)
es
)
es rc ge ou an S s R pt ins e ge ag ka rru P lt c te In Pa Vo I/O
ol (V
ts
)
PIC16C64X & PIC16C66X
PIC16C84 PIC16F84(1) 10 10 10 10 -- -- 512 36 64 512 -- -- 36 64 -- -- 1K 68 64 1K -- -- 68 64 PIC16CR84(1) PIC16F83(1) PIC16CR83(1)
10
--
1K
--
36
64
13 13 13 13 13
2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability. All PIC16C8X family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local sales office for availability of these devices.
(c) 1996 Microchip Technology Inc.
E.7
(c) 1996 Microchip Technology Inc. Clock
z) on H (M
Memory
or
M u od le
Peripherals
(s )
Features
ne ls
y
PIC16C9XX Family Of Devices
g in m m p M 2C C ) r O ra ts t) og tes) of /I PW t ol bi og Pr s e/ SPI y or cy 8(V ) Pr r e s P et l (b e en r( rc pa s) ( ia e( es qu ry ve ng rte m le ou ul ( er e o t a e la u S s tR s Fr R od Co Por tS nv in od em lS pt ins ou ge e/ ui M um M M ge rM lle nCo tP O rc ur rial ka rru i P e im c D ra ta R lta pt D te pu ow m -C ax Pa Se In A/ LC Pa I/O In Da Vo Ti EP M In Br Ca
er i at
am
em M
,U
R SA
T)
n ha
PIC16C923 4K 4 Com 32 Seg 176 TMR0, 1 SPI/I2C TMR1, TMR2 -- 5 9 25 27
8
4K
176 TMR0, 1 SPI/I2C TMR1, TMR2
--
--
4 Com 32 Seg
8
25
27
3.0-6.0 3.0-6.0
Yes Yes
-- --
64-pin SDIP(1), TQFP, 68-pin PLCC, DIE 64-pin SDIP(1), TQFP, 68-pin PLCC, DIE
PIC16C924
8
Note
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16CXX Family devices use serial programming with clock pin RB6 and data pin RB7. 1: Please contact your local Microchip representative for availability of this package.
PIC16C64X & PIC16C66X
DS30559A-page 123
E.8
)
(M
Hz
n
io
y
(W or
ds
)
at
or
pe r
M
em
es
)
by t
O
(
T)
) ts s ly pt es ol tip (V ru rc ul e ns tr
of
y
y
am
or
og r
)
SA R
en c
Pr
u
em
(s
le
)(
U
uc t
io
ns
M
eq
te r
M
Fr
ta
rt( s
In
So u
ng
od u
o
re
Ra
of I
M
um
Da
al
pt
lP
ns
r
ru
M
ge
RO
im
er M
dw a
r
er n
Pi
AM
m
ax
RO
xt
te r
lta
be
EP
er ia
Ha
M
R
E
In
I/O
um
Ti
S
PIC17C42 25 25 25 25 25 8K 454 Yes -- 4K 454 Yes Yes Yes 4K -- 454 TMR0,TMR1, 2 2 TMR2,TMR3 Yes Yes Yes Yes Yes -- 2K 232 TMR0,TMR1, 2 2 TMR2,TMR3 Yes Yes Yes 11 11 11 11 2K -- 232 TMR0,TMR1, 2 2 TMR2,TMR3 Yes Yes Yes 11 33 33 33 33 33
25
2K
--
232
Ca p P tu W res M s
TMR0,TMR1, 2 2 TMR2,TMR3
Yes
--
Yes
11
33
4.5-5.5 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
Vo
55 58 58 58 58 58
N
40-pin DIP; 44-pin PLCC, MQFP 40-pin DIP; 44-pin PLCC, TQFP, MQFP 40-pin DIP; 44-pin PLCC, TQFP, MQFP 40-pin DIP; 44-pin PLCC, TQFP, MQFP
PIC16C64X & PIC16C66X
PIC17C42A
PIC17CR42
PIC17C43
PIC17CR43
PIC17C44
TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3
40-pin DIP; 44-pin PLCC, TQFP, MQFP 40-pin DIP; 44-pin PLCC, TQFP, MQFP
(c) 1996 Microchip Technology Inc.
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
P
ac k
ag
es
DS30559A-page 124
PIC17CXX Family of Devices
Clock
Memory
Peripherals
Features
PIC16C64X & PIC16C66X
PIN COMPATIBILITY
Devices that have the same package type and VDD, VSS and MCLR pin locations are said to be pin compatible. This allows these different devices to operate in the same socket. Compatible devices may only requires minor software modification to allow proper operation in the application socket (ex., PIC16C56 and PIC16C61 devices). Not all devices in the same package size are pin compatible; for example, the PIC16C62 is compatible with the PIC16C63, but not the PIC16C55. Pin compatibility does not mean that the devices offer the same features. As an example, the PIC16C54 is pin compatible with the PIC16C71, but does not have an A/D converter, weak pull-ups on PORTB, or interrupts.
TABLE E-1:
PIN COMPATIBLE DEVICES
Pin Compatible Devices Package 8-pin 18-pin 20-pin
PIC12C508, PIC12C509 PIC16C54, PIC16C54A, PIC16CR54A, PIC16C56, PIC16C58A, PIC16CR58A, PIC16C61, PIC16C554, PIC16C556, PIC16C558 PIC16C620, PIC16C621, PIC16C622, PIC16C710, PIC16C71, PIC16C711, PIC16F83, PIC16CR83, PIC16C84, PIC16F84A, PIC16CR84 PIC16C55, PIC16C57, PIC16CR57B PIC16C62, PIC16CR62, PIC16C62A, PIC16C63, PIC16C72, PIC16C73, PIC16C73A PIC16C64, PIC16CR64, PIC16C64A, PIC16C65, PIC16C65A, PIC16C74, PIC16C74A PIC17C42, PIC17CR42, PIC17C42A, PIC17C43, PIC17CR43, PIC17C44 PIC16C923, PIC16C924
28-pin 28-pin 40-pin
40-pin 64/68-pin
(c) 1996 Microchip Technology Inc.
DS30559A-page 125
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 126
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
INDEX
A
ADDLW Instruction ......................................................... 76 ADDWF Instruction ........................................................ 76 ANDLW Instruction ......................................................... 76 ANDWF Instruction ........................................................ 76 Architectural Overview ..................................................... 9 Assembler ........................................................................ 88 Code Examples Changing Prescaler (T0 to WDT) ........................ 45 Changing Prescaler (WDT to T0) ........................ 45 Indirect Addressing ................................................ 28 Initializing Comparator Module ............................ 49 Initializing PORTA .................................................. 29 Initializing PORTC .................................................. 34 Read-Modify-Write Instructions on an I/O Port . 38 Saving the STATUS and W Registers in RAM . 68 Voltage Reference Configuration ........................ 54 Code Protection .............................................................. 71 COMF Instruction ........................................................... 79 Comparator Configuration ............................................ 48 Comparator Interrupt ..................................................... 51 Comparator Module ....................................................... 47 Comparator Operation .................................................. 49 Comparator Reference .................................................. 49 Configuration Bits ........................................................... 56 Configuring the Voltage Reference ............................. 54
B
BCF Instruction ............................................................... 77 Bit Manipulation .............................................................. 74 Block Diagrams ............................................................... 30 Comparator Analog Input Mode .......................... 51 Comparator I/O Operating Modes ....................... 48 Comparator Output ................................................ 50 Crystal Operation ................................................... 57 External Brown-out Protection 1 .......................... 65 External Brown-out Protection 2 .......................... 65 External Clock Input Operation ............................ 57 External Parallel Cystal Oscillator ....................... 58 External Power-on Reset Circuit ......................... 65 External Series Crystal Oscillator ........................ 58 In-circuit Serial Programming ............................... 71 Interrupt Logic ......................................................... 66 On-chip Reset Circuit ............................................ 59 Parallel Slave Port, PORTD-PORTE .................. 39 PIC16C641 .............................................................. 10 PIC16C642 .............................................................. 10 PIC16C661 .............................................................. 11 PIC16C662 .............................................................. 11 PORTC (In I/O Port Mode) ................................... 34 PORTD (In I/O Port Mode) ................................... 35 PORTE (In I/O Port Mode) ................................... 37 RA1:RA0 pins .......................................................... 29 RA3 pin ..................................................................... 30 RA4 pin ..................................................................... 31 RB3:RB0 pins .......................................................... 32 RB7:RB4 pins .......................................................... 32 RC Oscillator ........................................................... 58 Single Comparator ................................................. 49 Timer0 ...................................................................... 41 Timer0/WDT Prescaler .......................................... 44 Voltage Reference ................................................. 53 Voltage Reference Output Buffer ........................ 54 Watchdog Timer ..................................................... 69 Brown-out Reset (BOR) ................................................ 60 BSF Instruction ............................................................... 77 BTFSC Instruction .......................................................... 77 BTFSS Instruction .......................................................... 78
D
Data Memory Organization .......................................... 18 DECF Instruction ............................................................ 79 DECFSZ Instruction ....................................................... 79 Development Support .................................................... 87 Development Tools ........................................................ 87 Device Drawings 28-Lead Ceramic CERDIP Dual In-line with Window (300 mil)) ....................................... 107 28-Lead Ceramic Dual In-Line with Window (JW) (300 mil) ................................................. 107 28-Lead Plastic Small Outline (SO) - Wide, 300 mil Body ....................................................... 106 28-Lead Skinny Plastic Dual In-Line (SP) 300 mil ................................................... 105 40-Lead Ceramic Dual In-Line with Window (JW) - (600 mil) ..................................... 108 40-Lead Plastic Dual In-Line (P) - 600 mil ....... 109 44-Lead Plastic Leaded Chip Carrier (L) Square ................................................... 110 44-Lead Plastic Quad Flatpack (PQ) - 10x10x2 mm Body 1.6/0.15 mm Lead Form ... 111
F
Family of Devices PIC14XXX ............................................................. 117 PIC16C5X ............................................................. 118 PIC16C64X ................................................................6 PIC16C66X ................................................................6 PIC16C6X ............................................................. 120 PIC16C7X ............................................................. 121 PIC16C8X ............................................................. 122 PIC16C9XX ........................................................... 123 PIC16CXXX .......................................................... 119 PIC17CXX ............................................................. 124 Fuzzy Logic Dev. System (fuzzyTECH(R)-MP) .... 87, 89
C
C Compiler (MPLAB-C) ................................................. 89 CALL Instruction ............................................................. 78 Clocking Scheme/Instruction Cycle ............................. 15 CLRF Instruction ............................................................. 78 CLRW Instruction ........................................................... 78 CLRWDT Instruction ...................................................... 79 CMCON Register ............................................................ 47
G
General Purpose Register File .................................... 18 GOTO Instruction ........................................................... 80
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 127
PIC16C64X & PIC16C66X
I
I/O Ports ........................................................................... 29 PORTA ..................................................................... 29 PORTB ..................................................................... 32 PORTC ..................................................................... 34 PORTD ..................................................................... 35 PORTE ..................................................................... 36 I/O Programming Considerations ................................ 38 ICEPIC In-Circuit Emulator ........................................... 87 ID Locations ..................................................................... 71 INCF Instruction .............................................................. 80 INCFSZ Instruction ......................................................... 80 In-Circuit Serial Programming ...................................... 71 Indirect Addressing, INDF and FSR Registers ......... 28 Instruction Flow/Pipelining ............................................ 15 Instruction Format ........................................................... 73 Instruction Set ADDLW .................................................................... 76 ADDWF .................................................................... 76 ANDLW .................................................................... 76 ANDWF .................................................................... 76 BCF ........................................................................... 77 BSF ........................................................................... 77 BTFSC ...................................................................... 77 BTFSS ...................................................................... 78 CALL ......................................................................... 78 CLRF ........................................................................ 78 CLRW ....................................................................... 78 CLRWDT .................................................................. 79 COMF ....................................................................... 79 DECF ........................................................................ 79 DECFSZ ................................................................... 79 GOTO ....................................................................... 80 INCF .......................................................................... 80 INCFSZ .................................................................... 80 IORLW ...................................................................... 80 IORWF ...................................................................... 81 MOVF ....................................................................... 81 MOVLW .................................................................... 81 MOVWF .................................................................... 81 NOP .......................................................................... 82 OPTION .................................................................... 82 RETFIE ..................................................................... 82 RETLW ..................................................................... 82 RETURN .................................................................. 83 RLF ........................................................................... 83 RRF ........................................................................... 83 SLEEP ...................................................................... 83 SUBLW ..................................................................... 84 SUBWF .................................................................... 84 SWAPF ..................................................................... 85 TRIS .......................................................................... 85 XORLW .................................................................... 85 XORWF .................................................................... 85 Section ...................................................................... 73 Summary Table ...................................................... 75 INT Interrupt .................................................................... 67 INTCON Register ........................................................... 23 Interrupts .......................................................................... 66 Comparator .............................................................. 51 PORTB Change ..................................................... 32 PSP Read-Write ..................................................... 39 RB0/INT ................................................................... 66 Section ..................................................................... 66 Timer0 ...................................................................... 41 Timer0, Timing ........................................................ 42 IORLW Instruction .......................................................... 80 IORWF Instruction ......................................................... 81
M
MOVF Instruction ........................................................... 81 MOVLW Instruction ........................................................ 81 MOVWF Instruction ....................................................... 81 MPASM Assembler .................................................. 87, 88 MPLAB-C C Compiler ................................................... 89 MPLAB-SIM Software Simulator ........................... 87, 89
N
NOP Instruction .............................................................. 82
O
One-Time-Programmable (OTP) Devices ................... 7 Opcode ............................................................................. 73 OPTION Instruction ....................................................... 82 OPTION Register ........................................................... 22 Oscillator Configurations ............................................... 57 Oscillator Start-up Timer (OST) ................................... 60
P
Package Marking Information ............................ 112, 113 Packaging Information ................................................. 105 Parallel Slave Port ......................................................... 35 Section ..................................................................... 39 Parity Error Reset (PER) ........................................ 60, 61 PCL ................................................................................... 74 PCL and PCLATH .......................................................... 27 PCON Register ......................................................... 26, 61 PICDEM-1 Low-Cost PIC16/17 Demo Board ..... 87, 88 PICDEM-2 Low-Cost PIC16CXX Demo Board ... 87, 88 PICDEM-3 Low-Cost PIC16C9XX Demo Board ...... 88 PICDEM-3 PIC16C9XX Low-Cost Demonstration Board ................................................................ 87 PICMASTER(R) High Performance In-Circuit Emulator ......................................... 87 PICSTART(R) Plus Entry Level Development System ............................................................. 87 PICSTART(R) Plus Entrvel Prototype Programmer .................................................... 87 PIE1 Register .................................................................. 24 Pin Compatible Devices .............................................. 125 Pin Functions RD7/PSP7:RD0/PSP0 .......................................... 14 RE0/RD ....................................................... 14, 39 RE1/WR ...................................................... 14, 39 RE2/CS ....................................................... 14, 39 PIR1 Register .................................................................. 25 Port RB Interrupt ............................................................ 67 PORTA ............................................................................. 29 PORTB ............................................................................. 32 PORTC Register ............................................................ 34 PORTD Register ............................................................ 35
DS30559A-page 128
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
PORTE Register ............................................................. 36 Ports Parallel Slave Port .................................................. 39 PORTA ..................................................................... 29 PORTB ..................................................................... 32 PORTC ..................................................................... 34 PORTD ..................................................................... 14 PORTE ..................................................................... 14 Power Control/Status Register (PCON) ..................... 61 Power-down Mode (SLEEP) ........................................ 70 Power-on Reset (POR) ................................................. 60 Power-up Timer (PWRT) ............................................... 60 Prescaler .......................................................................... 44 PRO MATE(R) Universal Programmer .......................... 87 Program Memory Organization .................................... 17 PSPMODE bit ........................................................... 35, 36 TRISA ............................................................................... 29 TRISB ............................................................................... 32 TRISC Register .............................................................. 34 TRISD Register .............................................................. 35 TRISE Register ............................................................... 36
V
Voltage Reference Module ........................................... 53 VRCON Register ............................................................ 53
W
Watchdog Timer (WDT) ................................................ 69
X
XORLW Instruction ........................................................ 85 XORWF Instruction ........................................................ 85
Q
Quick-Turnaround-Production (QTP) Devices ............ 7
LIST OF EXAMPLES
Example 3-1:Instruction Pipeline Flow ............................... 15 Example 4-1:Indirect Addressing........................................ 28 Example 5-1:Initializing PORTA ......................................... 29 Example 5-2:Initializing PORTC ......................................... 34 Example 5-3:Read-Modify-Write Instructions on an I/O Port .......................................................... 38 Example 6-1:Changing Prescaler (Timer0WDT)............. 45 Example 6-2:Changing Prescaler (WDTTimer0)............. 45 Example 7-1:Initializing Comparator Module ...................... 49 Example 8-1:Voltage Reference Configuration .................. 54 Example 9-1:Saving the STATUS and W Registers in RAM............................................................... 68
R
RA2 pin ............................................................................. 30 RC Oscillator ................................................................... 58 Reset ................................................................................ 59 RETFIE Instruction ......................................................... 82 RETLW Instruction ......................................................... 82 RETURN Instruction ...................................................... 83 RLF Instruction ................................................................ 83 RRF Instruction ............................................................... 83
S
Serialized Quick-Turnaround-Production (SQTP) Devices .............................................................. 7 SFR ................................................................................... 74 SFR As Source/Destination .......................................... 74 SLEEP Instruction .......................................................... 83 Software Simulator (MPLAB-SIM) ............................... 89 Special Features of the CPU ........................................ 55 Special Function Registers ..................................... 19, 74 Stack ................................................................................. 27 STATUS Register ........................................................... 21 SUBLW Instruction ......................................................... 84 SUBWF Instruction ......................................................... 84 SWAPF Instruction ......................................................... 85 Switching Prescalers ..................................................... 45
LIST OF FIGURES
Figure 3-1: Figure 3-2: Figure 3-3: Figure 4-1: Figure 4-2: Figure 4-3: Figure 4-4: Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: Figure 4-10: Figure 4-11: Figure 4-12: Figure 5-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 5-5: Figure 5-6: Figure 5-7: Figure 5-8: Figure 5-9: Figure 5-10: Figure 5-11: Figure 5-12: Figure 6-1: Figure 6-2: Figure 6-3: PIC16C641/642 Block Diagram..................... 10 PIC16C661/662 Block Diagram..................... 11 Clock/Instruction Cycle .................................. 15 PIC16C641/661 Program Memory Map and Stack.............................................................. 17 PIC16C642/662 Program Memory Map and Stack.............................................................. 17 PIC16C641/661 Data Memory Map .............. 18 PIC16C642/662 Data Memory Map .............. 19 STATUS Register (Address 03h, 83h) .......... 21 OPTION Register (address 81h) ................... 22 INTCON Register (address 0Bh, 8Bh) .......... 23 PIE1 Register (address 8Ch)......................... 24 PIR1 Register (address 0Ch) ........................ 25 PCON Register (Address 8Eh)...................... 26 Loading Of PC In Different Situations............ 27 Direct/indirect Addressing.............................. 28 Block Diagram of RA1:RA0 Pins ................... 29 Block Diagram of RA2 Pin ............................. 30 Block Diagram of RA3 Pin ............................. 30 Block Diagram of RA4 Pin ............................. 31 Block Diagram of RB7:RB4 Pins ................... 32 Block Diagram of RB3:RB0 Pins ................... 32 PORTC Block Diagram (in I/O port Mode) .... 34 PORTD Block Diagram (in I/O Port Mode) .... 35 TRISE Register (Address 89h) ...................... 36 PORTE Block Diagram (in I/O Port Mode) .... 37 Successive I/O Operation.............................. 38 PORTD and PORTE as a Parallel Slave Port 39 Timer0 Block Diagram ................................... 41 Timer0 Timing: Internal Clock/No Prescaler.. 41 Timer0 Timing: Internal Clock/Prescale 1:2... 42
T
Timer Modules Timer0 Block Diagram ................................................. 41 Counter Mode ................................................. 41 External Clock ................................................. 43 Interrupt ............................................................ 41 Prescaler .......................................................... 44 Section ............................................................. 41 Timer Mode ..................................................... 41 Timing Diagram .............................................. 41 TMR0 register ................................................. 41 Timing Diagrams and Specifications .......................... 98 TMR0 Interrupt ................................................................ 67 TRIS Instruction .............................................................. 85
(c) 1996 Microchip Technology Inc.
Preliminary
DS30559A-page 129
PIC16C64X & PIC16C66X
Figure 6-4: Figure 6-5: Figure 6-6: Figure 7-1: Figure 7-2: Figure 7-3: Figure 7-4: Figure 7-5: Figure 8-1: Figure 8-2: Figure 8-3: Figure 9-1: Figure 9-2: Timer0 Interrupt Timing.................................. 42 Timer0 Timing With External Clock................ 43 Block Diagram of the Timer0/WDT Prescaler 44 CMCON Register (Address 1Fh) ................... 47 Comparator I/O Operating Modes.................. 48 Single Comparator ......................................... 49 Comparator Output Block Diagram ................ 50 Analog Input Model ........................................ 51 VRCON Register(Address 9Fh) ..................... 53 Voltage Reference Block Diagram ................. 53 Voltage Reference Output Buffer Example .... 54 Configuration Word ........................................ 56 Crystal Operation (or Ceramic Resonator) (HS, XT or LP Osc Configuration).................. 57 External Clock Input Operation (HS, XT or LP Osc Configuration).................. 57 External Parallel Resonant Crystal Oscillator Circuit ............................................................. 58 External Series Resonant Crystal Oscillator Circuit ............................................................. 58 RC Oscillator Mode ........................................ 58 Simplified Block Diagram of On-chip Reset Circuit ............................................................. 59 Brown-out Situations ...................................... 60 Time-out Sequence on Power-up (MCLR not tied to VDD): Case 1 ....................................... 64 Time-out Sequence on Power-up (MCLR not tied to VDD): Case 2 ....................................... 64 Time-out Sequence on Power-up (MCLR tied to VDD) ............................................................... 64 External Power-on Reset Circuit (For Slow VDD Power-up) ...................................................... 65 External Brown-out Protection Circuit 1 ......... 65 External Brown-out Protection Circuit 2 ......... 65 Interrupt Logic ................................................ 66 RB0/INT Pin Interrupt Timing ......................... 67 Watchdog Timer Block Diagram .................... 69 Summary of Watchdog Timer Registers ........ 69 Wake-up from Sleep Through Interrupt ......... 70 Typical In-Circuit Serial Programming Connection ..................................................... 71 General Format for Instructions ..................... 73 Load Conditions ............................................. 97 External Clock Timing .................................... 98 CLKOUT and I/O Timing ................................ 99 Reset, Watchdog Timer, Oscillator Start-Up Timer, and Power-Up Timer Timing ................... 100 Brown-out Reset Timing .............................. 100 Timer0 Clock Timing .................................... 101 Parallel Slave Port Timing (PIC16C661 and PIC16C662) ................................................. 102 Table 5-6: Table 5-7: Table 5-8: Table 5-9: Table 5-10: Table 5-11: Table 6-1: Table 7-1: Table 8-1: Table 9-1: Table 9-2: Table 9-3: Table 9-4: Table 9-5: Table 9-6: Table 10-1: Table 10-2: Table 11-1: Table 12-1: Summary of Registers Associated with PORTC .......................................................... 34 PORTD Functions.......................................... 35 Summary of Registers Associated with PORTD .......................................................... 35 PORTE Functions.......................................... 37 Summary of Registers Associated with PORTE .......................................................... 37 Registers Associated with Parallel Slave Port39 Registers Associated with Timer0 ................. 45 Registers Associated with Comparator Module ....................................... 52 Registers Associated with Voltage Reference54 Capacitor Selection for Ceramic Resonators (Preliminary) .................................................. 57 Capacitor Selection for Crystal Oscillator (Preliminary) .................................................. 57 Time-out in Various Situations....................... 61 Status Bits and Their Significance ................. 62 Initialization Condition for Special Registers.. 62 Initialization Condition for Registers .............. 63 Opcode Field Descriptions............................. 73 Instruction Set................................................ 75 Development Tools From Microchip .............. 90 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) ................................... 91 Comparator Specifications............................. 96 Voltage Reference Specifications.................. 96 External Clock Timing Requirements ............ 98 CLKOUT and I/O Timing Requirements ........ 99 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Reset Requirements ................................................... 100 Timer0 Clock Requirements ........................ 101 Parallel Slave Port Requirements (PIC16C661 and PIC16C662) .......................................... 102 Pin Compatible Devices............................... 125
Figure 9-3: Figure 9-4: Figure 9-5: Figure 9-6: Figure 9-7: Figure 9-8: Figure 9-9: Figure 9-10: Figure 9-11: Figure 9-12: Figure 9-13: Figure 9-14: Figure 9-15: Figure 9-16: Figure 9-17: Figure 9-18: Figure 9-19: Figure 9-20: Figure 10-1: Figure 12-1: Figure 12-2: Figure 12-3: Figure 12-4: Figure 12-5: Figure 12-6: Figure 12-7:
Table 12-2: Table 12-3: Table 12-4: Table 12-5: Table 12-6:
Table 12-7: Table 12-8: Table E-1:
LIST OF TABLES
Table 1-1: Table 3-1: Table 3-2: Table 4-1: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 5-5: PIC16C64X & PIC16C66X Device Features ... 6 PIC16C641/642 Pinout Description ............... 12 PIC16C661/662 Pinout Description ............... 13 Special Function Registers ............................ 20 PORTA Functions .......................................... 31 Summary of Registers Associated With PORTA........................................................... 31 PORTB Functions .......................................... 33 Summary of Registers Associated with PORTB........................................................... 33 PORTC Functions .......................................... 34
DS30559A-page 130
Preliminary
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
ON-LINE SUPPORT
Microchip provides two methods of on-line support. These are the Microchip BBS and the Microchip World Wide Web (WWW) site. Use Microchip's Bulletin Board Service (BBS) to get current information and help about Microchip products. Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts. To provide you with the most responsive service possible, the Microchip systems team monitors the BBS, posts the latest component data and software tool updates, provides technical help and embedded systems insights, and discusses how Microchip products provide project solutions. The web site, like the BBS, is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. The procedure to connect will vary slightly from country to country. Please check with your local CompuServe agent for details if you have a problem. CompuServe service allow multiple users various baud rates depending on the local point of access. The following connect procedure applies in most locations. 1. Set your modem to 8-bit, No parity, and One stop (8N1). This is not the normal CompuServe setting which is 7E1. 2. Dial your local CompuServe access number. 3. Depress the key and a garbage string will appear because CompuServe is expecting a 7E1 setting. 4. Type +, depress the key and "Host Name:" will appear. 5. Type MCHIPBBS, depress the key and you will be connected to the Microchip BBS. In the United States, to find the CompuServe phone number closest to you, set your modem to 7E1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. After the system responds with "Host Name:", type NETWORK, depress the key and follow CompuServe's directions. For voice information (or calling from overseas), you may call (614) 723-1550 for your local CompuServe number. Microchip regularly uses the Microchip BBS to distribute technical information, application notes, source code, errata sheets, bug reports, and interim patches for Microchip systems software products. For each SIG, a moderator monitors, scans, and approves or disapproves files submitted to the SIG. No executable files are accepted from the user community in general to limit the spread of computer viruses.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp.mchip.com/biz/mchip The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world.
Connecting to the Microchip BBS
Connect worldwide to the Microchip BBS using either the Internet or the CompuServe(R) communications network.
Internet:
You can telnet or ftp to the Microchip BBS at the address: mchipbbs.microchip.com
Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER, and are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM, MPLAB, PRO MATE, and fuzzyLAB, are trademarks and SQTP is a service mark of Microchip in the U.S.A.
CompuServe Communications Network:
When using the BBS via the Compuserve Network, in most cases, a local call is your only expense. The Microchip BBS connection does not use CompuServe membership services, therefore you do not need CompuServe membership to join Microchip's BBS. There is no charge for connecting to the Microchip BBS.
fuzzyTECH is a registered trademark of Inform Software Corporation. IBM, IBM PC-AT are registered trademarks of International Business Machines Corp. Pentium is a trademark of Intel Corporation. Windows is a trademark and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated.
All other trademarks mentioned herein are the property of their respective companies.
(c) 1996 Microchip Technology Inc.
DS30559A-page 131
This document was created with FrameMaker 4 0 4
PIC16C64X & PIC16C66X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? PIC16C64X & PIC16C66X Questions: Device: Y N Literature Number: DS30559A FAX: (______) _________ - _________
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30559A-page 132
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
NOTES:
(c) 1996 Microchip Technology Inc.
DS30559A-page 133
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 134
(c) 1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
PIC16C64X & PIC16C66X PRODUCT IDENTIFICATION SYSTEM
PART NO. -XX X /XX XXX Pattern: Package: Special Requirements SO L P TQ SP JW I E 04 10 20 = = = = = = = = = = = = SOIC PLCC PDIP TQFP Skinny DIP Windowed DIP 0C to +70C -40C to +85C -40C to +125C 4 MHz 10MHz 20 MHz Examples
a) PIC16C662-04/P Commercial Temp., PDIP Package, 4 MHz, normal VDD limits PIC16C662-04I/SO Industrial Temp., SOIC package, 4 MHz, normal VDD limits PIC16C662-04E/P Automotive Temp., PDIP package, 4 MHz, normal VDD limits
b)
Temperature Range: Frequency Range:
c)
Device
Please contact your local sales office for exact ordering procedures. JW devices are UV erasable and can be programmed to any device configuration. JW devices meet the electrical requirements of each oscillator type (including LC devices).
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office (see below) 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
(c) 1996 Microchip Technology Inc.
DS30559A-page 135
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com
AMERICAS (continued)
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific Unit 2101, Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
Taiwan, R.O.C
Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575
EUROPE
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5858 Fax: 44-118 921-5835
Beijing
Microchip Technology, Beijing Unit 915, 6 Chaoyangmen Bei Dajie Dong Erhuan Road, Dongcheng District New China Hong Kong Manhattan Building Beijing 100027 PRC Tel: 86-10-85282100 Fax: 86-10-85282104
Chicago
Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
India
Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
Denmark
Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
Dallas
Microchip Technology Inc. 4570 Westgrove Drive, Suite 160 Addison, TX 75248 Tel: 972-818-7423 Fax: 972-818-2924
Japan
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
France
Arizona Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Dayton
Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc. Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934
Germany
Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Munchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Los Angeles
Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
Italy
Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
11/15/99
Shanghai
Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
New York
Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
All rights reserved. (c) 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.

▲Up To Search▲

Price & Availability of PIC16C641-04ITQ

	To Download PIC16C641-04ITQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .